A multi-core processor is a central processor that contains two or more computational cores on a single processor chip or in the same package .
Terminology
In English, there are two commonly used terms for processors with multiple cores: multi-core and many-core .
The term multi-core ( multi-core [1] ) is usually applied to central processors containing two or more general-purpose cores , but is sometimes also used for digital signal processors (DSP) and single-chip systems (SoC, SoC). By multi-core processor, it is understood that several cores are integrated into one integrated circuit (manufactured on a single silicon chip). If several semiconductor crystals were combined into one case , then the design is called a multi-chip module (the multi-chip module , MCM).
The term multiprocessor refers to computers that have several physically separate processors (for example, server motherboards often have 2 or 4 sockets for connecting multiple chips), but managed by a single instance of the operating system (OS).
The concept of multi-core [1] ( English many-core [2] or massively multi-core ) can be used to describe multi-core systems with a high number of cores from tens to hundreds or more. For example, it is the name “multi-core” (“many-core”) that was used by Intel for the Intel MIC computer [3] .
Single-chip multiprocessor, on-chip multiprocessor, chip multiprocessing, CMP - so the early researchers called their projects of placing multiple processors on the same substrate [4] [5] [6] .
Multi- System Architecture
The architecture of multi-core processors largely repeats the architecture of symmetric multiprocessors ( SMP-machines ) only on a smaller scale and with its own features.
The first multi-core processors ( first generation CMP ) were the simplest circuits: two processor cores placed on a single chip without sharing any resources other than the memory bus (for example, Sun UltraSPARC IV and Intel Pentium D ). A “true multi-core” ( second generation CMP ) processor is considered to be when its compute cores share a third or second level cache: for example, the Sun UltraSPARC IV +, Intel Core Duo, and all modern multi-core processors.
In multi-core processors, the clock frequency is usually intentionally reduced. This allows you to reduce the power consumption of the processor without loss of performance: power consumption grows like a cube from the increase in the frequency of the processor. Doubling the number of processor cores and halving their clock frequency, you can get almost the same performance, while the power consumption of such a processor will decrease by 4 times.
In some processors, the clock frequency of each core may vary depending on its individual load. The kernel is a full-fledged microprocessor that uses all the achievements of microprocessor technology: pipelines , extraordinary code execution, multilevel cache , support for vector commands .
Superscalarity in the core is not always present if, for example, the processor manufacturer seeks to simplify the core as much as possible.
Each core can use temporal multithreading technology or, if it is superscalar, SMT technology for simultaneous execution of several threads , creating the illusion of several “logical processors” based on each core. On Intel processors, this technology is called Hyper-threading and doubles the number of logical processors compared to physical ones. On Sun UltraSPARC T2 processors (2007), this increase can reach 8 threads per core.
Multi-core processors can be divided by the presence of support for coherence (shared) cache memory between cores. There are processors with such support and without it. The method of communication between the cores:
- shared tire;
- network (Mesh) on point-to-point channels;
- network with a switch;
- shared cache memory .
Cache memory: In all current multi-core processors, each core separately has a level 1 cache, and level 2 cache exists in several ways:
- shared - is located on the same crystal with the cores and is available to each of them in full. Used in Intel Core processor families;
- individual - individual caches of equal volume, integrated into each of the cores. Data exchange from level 2 caches between the cores takes place via a memory controller - integrated ( Athlon 64 X2 , Turion X2 , Phenom ) or external (used in Pentium D , later, Intel abandoned this approach).
Multicore processors also have a homogeneous or heterogeneous architecture:
- homogeneous architecture - all processor cores are the same and perform the same tasks. Typical examples: Intel Core Duo , Sun SPARC T3 , AMD Opteron ;
- heterogeneous architecture - the processor cores perform different tasks. A typical example is the Cell processor of the IBM , Sony and Toshiba alliance, of which one of the nine cores is the core of the general-purpose PowerPC processor , and the other eight are specialized processors optimized for vector operations used in the Sony PlayStation 3 game console.
Productivity
In applications optimized for multi-threading , there is a performance boost on a multi-core processor. However, if the application is not optimized, then it will not receive virtually any benefit from additional cores, and may even run slower than on a processor with a smaller number of cores, but a higher clock frequency . These are mainly applications developed before the advent of multi-core processors, or applications that, in principle, do not use multi-threading.
Most operating systems allow you to run multiple applications at the same time . This results in performance gains, even if the applications are single-threaded.
Increasing the number of cores
Today, many processor manufacturers, in particular, Intel , AMD , IBM , ARM , further increase the number of processor cores recognized as one of the priority areas for increasing performance.
History of Mass Multi-Core Processors
POWER
The first processor, designed for mass use, and not for embedded systems , was POWER4 with two PowerPC cores on a single chip, released by IBM in 2001.
The 2-core IBM PowerPC-970MP ( G5 ) was introduced in 2005. This processor was equipped with the latest Power Mac G5 .
SPARC
In March 2004, Sun Microsystems introduced the first 2-core processor architecture SPARC: UltraSPARC IV - the first generation CMP. The second-generation CMP processor was the UltraSPARC IV + (mid-2005), where the two processor cores shared off-chip cache level 3 and on-chip cache level 2.
Fujitsu in its line of SPARC64 introduced a 2-core processor SPARC64 VI only in 2007.
x86
In April 2005, AMD launched the AMD64 2-core Opteron processor designed for servers .
In May 2005, Intel released the Pentium D processor architecture x86-64 , which became the first 2-core processor designed for personal computers. This was Intel’s “quick” response to AMD’s challenge. In fact, the Pentium D, built on the basis of Intel's leading architecture, NetBurst , consisted of two separate processors placed on one substrate, without any common elements. Since Intel abandoned the architecture of NetBurst in late 2005, Pentium D did not develop. This multi-core Core Duo processor on a more economical Core architecture was released by Intel in January 2006.
In March 2010, the first 12-core serial processors appeared, which were AMD's Opteron 6100 server processors ( x86 / x86-64 architecture ). [7]
In 2011, AMD mastered the production of 8-core processors for home computers [8] and 16-core for server systems [9] .
In August 2011, AMD launched the first 16-core Opteron Series 6200 Series Server Processors (codenamed Interlagos ). The Interlagos processor combines two 8-core (4-module) chips in one package and is fully compatible with the existing AMD Opteron 6100 series platform ( Socket G34 ). [ten]
As of 2016, Intel is releasing processors for Xeon E7 servers - with 4 to 24 cores. [11] [12] (E5 up to 22 cores).
A summary of the history of microprocessors and their parameters are presented in an updated English article: Chronology of microprocessors , 2010s . To get the number of processor cores, multiply the Cores per die and Dies per module fields, to get the number of hardware threads, multiply the number of cores by the number of threads per core. For example, for Xeon E7, Intel: “4, 6, 8, 10” cores per 1 die per 1-2 hardware streams = maximum 10 cores and 20 hardware streams, AMD FX “Bulldozer” Interlagos “4-8” per 2 per 1 = maximum of 16 cores and 16 threads.
The history of experimental multicore processors
On September 27, 2006, at the IDF Fall developer forum, Intel demonstrated an experimental 80 nuclear chip with a capacity of up to 1 TFLOPS. Each core worked with a clock frequency of 3.16 GHz, the power consumption of the chip reached about 100 W [13] .
August 20, 2007 the company Tilera , announced the chip TILE64 with 64 processor cores and an integrated high-performance network through which data can be exchanged between different cores at speeds up to 32 Tbps. [14] [15]
On October 26, 2009, Tilera announced [16] the TILE-Gx series 100-core general-purpose processor ( eng. ). Each processor core is a separate processor with 1 and 2 level cache memory . The cores, memory, and system bus are interconnected using a mesh network topology. Processors are manufactured on 40-nm process technology and operate at a clock frequency of 1.5 GHz. The release of 100-core processors is scheduled for early 2011.
On December 2, 2009, Intel introduced a single-chip " cloud-based " Single-chip Cloud Computer (SCC) computer, which is a 48-core chip. The " cloudiness " of the processor is that all 48 cores communicate with each other as network nodes. SCC is part of a project whose goal is to create a 100-core processor [17] .
In June 2011, Intel revealed the details of the Many Integrated Core (MIC) architecture being developed - this technology grew out of the Larrabee project. Microprocessors based on this architecture will receive more than 50 micro-cores of the x86 architecture and will be manufactured in 2012 using the 22-nm process technology. These microprocessors cannot be used as a central processor , but from several chips of this architecture computing accelerators will be built as a separate expansion card and compete in the GPGPU and high-performance computing markets with solutions like Nvidia Tesla and AMD FireStream . [18] According to the description of the architecture published in 2012, chips with up to 60 cores are possible.
In October 2011, the company Adapteva introduced the 64-core microprocessor Epiphany IV which show performance up to 70 gigaflops (SP), while consuming less than 1 watt of electricity. The microprocessors are designed using the RISC architecture and, familiarization samples were planned to be produced in 2012 using the 28-nm GlobalFoundries process technology. These processors can not be used as a central processor , but the company Adapteva suggests using them as a coprocessor for such complex tasks as face recognition or user gestures. The company Adapteva claims that in the future the number of cores of this microprocessor can be increased to 4096. It is planned that the 4096-core processor in the main version (700 MHz) is estimated to provide 5.6 TFLOPS, consuming only 80 watts.
[19] [20] .
In January 2012, the company ZiiLabs (a subsidiary of Creative Technology ) announced a 100-core system on a ZMS-40 chip. This system combines a 4-core 1.5 GHz ARM Cortex-A9 processor (with Neon multimedia blocks) and an array of 96 simpler and less universal StemCell computing cores. StemCell cores are SIMD energy efficient architecture, peak performance in floating point calculations (32 bits) is 50 gigaflops , whose cores work more like a GPU in other systems on a chip and can be used to process video, image and audio to accelerate 3D - and 2D graphics and other multimedia tasks (supported by OpenGL ES 2.0 and OpenCL 1.1) [21] .
Multi-core controllers
There is also a tendency to introduce multi-core microcontrollers into mobile devices .
For example:
- seaForth-24 [22] is a new development of the multi-core MISC architecture of Chuck Moore : 1 GHz 24-core asynchronous controller.
- The controller from Parallax [23] has eight 32-bit processors (COG) in a single P8X32A chip.
- Kilocore PowerPC -processor with 1024 8-bit cores operating at 125 MHz. At the moment there is a 256-core processor.
See also
- Microprocessor core
- Multiprocessing
- Multithreading
- Hyper-threading
- Tylera
- Intel larrabee
Notes
- ↑ 1 2 The Crisis of a Parallel World , Sergey Kuznetsov: Review of the December 2009 issue of Computer magazine (IEEE Computer Society, V. 42, No 12, December, 2009): “multi-core (multicore) and multi-core (many-core) processor architectures”
- ↑ Programming Many-Core Chips. By András Vajda , page 3
- ↑ [1] : "for which you have introduced this new term instead of the usual multi-core,"
- Case The Case for a Single-Chip Multiprocessor - Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang - Appears in Proceedings Seventh International Symp. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), Cambridge, MA, October 1996
- ↑ Stanford Hydra Single-Chip Multiprocessor (not available link) . The date of circulation is September 4, 2016. Archived August 29, 2007.
- ↑ ChipMultiprocessor Architecture: Kunle Olukotun, Lance Hammond, James Laudon - 2007
- AMD "AMD gave the green light to the 8- and 12-core Opteron 6100 series processors" - overclockers.ua
- 3D 3DNews website: “Official AMD Processors AMD FX Announcement”
- 3D 3DNews website: “AMD has begun a massive supply of server Bulldozer. Desktop postponed? " .
- 3D 3DNews website: “Data on AMD AMD Bulldozer: 3 GHz maximum?” .
- ↑ Intel® Xeon® Processor E7 Family
- ↑ Intel unleashes new Xeon E7 v4 CPUs including 24-core monster | Techradar
- ↑ Intel has demonstrated an 80-core superprocessor of the future . Lenta.ru (September 27, 2006). The appeal date is August 13, 2010. Archived on March 2, 2012.
- ↑ Article on the website 3dnews.ru: "Tilera Tile64 - a chip with 64 processor cores"
- "Tilera Processor: The World's Highest Performance Embedded Processor" (not available link) . The appeal date is October 19, 2018. Archived March 23, 2010.
- ↑ Modnews
- ↑ Article on lenta.ru: “Intel demonstrated a 48-core processor”
- 3D 3DNews website: "Intel MIC: 22nm Knights Corner - in 2012, ExaScale - in 2018"
- 3D 3DNews website: “Adapteva's 64-core chip can be used in smartphones and tablets” , 10/05/2011
- ↑ Adapteva will soon start delivering evaluation samples of 28-nm 64-core E64G4 processors // Ixbt.com, March 21, 2012
- 3D 3DNews website: “ZiiLabs introduced the 4 + 96-core ZMS-40 processor”
- ↑ Archived copy (inaccessible link) . The appeal date is April 15, 2008. Archived July 21, 2011.
- ↑ Propeller | Parallax inc
Literature
- (1999) Processor Architecture - From Dataflow to Superscalar and Beyond ( ISBN 3540647988 ) (Eng.)
- Kunle Olukotun . Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency . - Morgan and Claypool Publishers, 2007. - 154 p. - ISBN 159829122X . (eng.)
- (2008) OpenSPARC Internals ( ISBN 0557019745 ) (English)
- (2009) Microprocessor Architecture - From Simple Pipelines to Chip Multiprocessors ( ISBN 0521769922 ) (English)
- Multi-core processors. Training course. A.V. Kalachev ISBN 978-5-9963-0349-6
- Mario Nemirovsky, Dean M. Tullsen. Multithreading Architecture. - Morgan and Claypool Publishers, 2013. - 1608458555 p. - ISBN 1608458555 . (eng.)
Links
- Intel and AMD dual-core processors: theory: part 1 , part 2 // Ferra.ru , June 2005
- Vyacheslav Lyubchenko, Yuri Tyazhlov Caution: multi-core processor // Osp.ru , June 2007
- Multi-core processors / retrospectives since 2005 /: Six-core processors Intel Core i5 and Core i7 (Coffee Lake) // IXBT.com , Oct 2017