The pulse number counter is a device whose outputs produce a binary ( binary-decimal ) code, determined by the number of incoming pulses. Counters can be built on two-stage D-triggers , T-triggers and JK-triggers .
The main parameter of the counter - the counting module - the maximum number of single signals that can be counted by the counter. Counters denote by ST (from the English. Counter).
Content
Classification
Counters classify:
- by the number of steady states of triggers
- on binary triggers
- on ternary triggers [1]
- on n-ary triggers
- modulo account:
- binary decimal ( decade );
- binary;
- with an arbitrary permanent counting module;
- with variable counting module;
- in the direction of the account:
- summing;
- deducting;
- reversible;
- according to the method of forming internal relations:
- with sequential carry;
- with accelerated transfer;
- with parallel accelerated transfer;
- with the through accelerated transfer;
- with combined transfer;
- annular;
- By way of switching the trigger:
- synchronous;
- asynchronous;
- Johnson Counter [2]
Binary Counters
A binary counter scheme can be obtained using formal synthesis , but heuristic is a more obvious way. Binary Counter Truth Table - a sequence of binary numbers from zero to where n is the digit capacity of the counter. The observation of the digits of the numbers that make up the table leads to an understanding of the block diagram of the binary counter. The states of the low-order digit when viewed in the corresponding column of the table show the alternation of zeros and units of the form 01010101 ..., which is natural, since the low-order bit receives an input signal and switches from each input. In the next discharge there is a sequence of pairs of zeros and units of the form 00110011 .... In the third bit, a sequence of fours of zeros and ones 00001111 ... is formed, etc. From this observation, it is clear that the next most significant digit switches with a frequency that is two times smaller than the current one.
It is known that the counting trigger divides the frequency of the input pulses into two. Comparing this fact with the above regularity, we see that the counter can be built in the form of a chain of successively included counting triggers. Note, by the way, that according to GOST, the inputs of the elements are depicted on the left, and the outputs on the right. Compliance with this rule leads to the fact that in the number contained in the meter, the lower digits are located to the left of the older ones.
Binary counters with parallel carry and adjacent coding
Above, we consider the schemes of binary sequential counters, that is, such counters in which when the state of a certain trigger changes, a subsequent trigger is triggered, and the triggers change their states not sequentially, but sequentially. If in this situation you have to change your states of n triggers, then to complete this process you will need n time intervals corresponding to the time of state change of each of the triggers. Such a consistent nature of work is the cause of two shortcomings of a sequential counter: a lower counting rate compared to parallel counters and the possibility of the appearance of spurious signals at the output of the circuit. In parallel counters, the synchronizing signals are sent to all triggers simultaneously.
The sequential nature of the transitions of the counter triggers is the source of spurious signals at its outputs. For example, in a four-digit counter, leading the account in the usual four-digit binary code with "weights" of digits 8-4-2-1, when switching from to the state the output will be the following sequence of states:
This means that during the transition from state 7 to state 8, codes corresponding to states 6 will appear on the counter inputs for a short time; four; 0. The change of these intermediate states can cause false operation of other logic circuits, for example, if a decoder is connected to such a counter, then at its outputs 0, 4, 6 there can be briefly active states that can falsely change the states connected to them at the inputs of other triggers - this undesirable phenomenon is called logical "racing" or "racing signals." You can eliminate races by applying counters with neighboring or anti-coding coding of states, for example, counting in the reflexive Gray code .
In order to reduce the time course of transients, it is possible to implement a counter in the variant with supplying input counting pulses simultaneously to all triggers. In this case, we obtain a counter with parallel transfer.
According to the schemes of parallel-transfer meters, counters are built, the switching delay of one trigger in which is commensurate with the period of the counted pulses.
An example . If the switching delay of one trigger is 30 ns, then when building a counter according to a scheme with sequential transfer of more than four digits working in a regular binary code, when the counting pulses period is 120 ns and below, counting fails begin, the transfer does not have time to spread along the chain of triggers before the next counting momentum.
In the parallel transfer meters, the information inputs of the triggers are given signals that are a logical function of the counter state and determine the specific triggers that must change their state for a given input pulse. The principle of gating is as follows: a trigger changes its state when a next synchronization pulse is passed, if all previous triggers were in a state of logical one.
Parallel counters have a higher speed than sequential ones, since the logic function of the current state of the counter and the counting pulse is sent to the switching inputs of all triggers simultaneously.
Synchronous counters with parallel transfer have the maximum speed; we will find the structure heuristically, having considered the processes of adding one to binary numbers and subtracting it from them.
Serial-to-parallel counters
In connection with the restrictions on the construction of meters with parallel transfer of large bit width, meters with a group structure, or meters with a series-parallel transfer, are widely used. Discharges of such counters are divided into groups within which the principle of parallel transfer is organized. The groups themselves are connected in series with the use of conjunctors , which form the transfer to the next group with a single state of all the previous triggers. With a single state of all the group triggers, the arrival of the next input signal will create a transfer from this group. This situation prepares the intergroup conjunctor for direct transmission of the input signal to the next group.
In the worst case for speed, when the transfer passes through all groups and enters at the last input,
- t SET = t • (ĺ - 1) + t GR ,
where ĺ is the number of groups, t ГР is the time to establish the code in the group.
In the developed series of ICs, there are usually 5 ... 10 variants of binary counters, made in the form of four-digit groups (sections). Cascading sections can be performed by their sequential switching along transfer chains, organization of parallel-sequential transfers or for more complex counters with two additional control inputs for counting and transfer resolution by organizing parallel transfers both in and between groups.
A special feature of synchronous type binary counters is the presence of situations with simultaneous switching of all its digits (for example, for a summing counter when switching from code combination 11 ... 1 to combination 00 ... 0 when the counter overflows and generating a transfer signal). Simultaneous switching of many triggers creates a significant current pulse in the power supply circuits of the control center and can lead to failure in their work. Therefore, in the guidelines on the use of some LSI / VLSI programmable logic, in particular, there is a limit on the width of binary counters by a given value of k (for example, 16). If it is necessary to use a higher bit counter, it is recommended to switch to the Gray code, for which transitions from one code combination to another are accompanied by switching only one digit. True, in order to obtain the result of the counting in binary code, an additional code converter will have to be used, but this is a payment for getting rid of high-intensity current pulses in the power supply circuits.
See also
- Decatron
- Frequency divider
- Timer
- Electronic pulse counter
- Adder
Notes
- ↑ A.S.Galkin, V.P.Gribok and V.M. Kazakov . Ring counter on potential logic elements , Binary coded ternary / AC SU1466009 .
- ↑ Counters. Johnson counter.