Logical Labor

Logical labor costs , logical effort method ( logical effort, method of logical effort ) is a term coined by Ivan Sutherland and Bob Sproul in 1991 in the description of the method they developed for estimating time delay in CMOS logic elements. The method allows you to choose the optimal configuration of logic circuits to perform a specific logical function and scale logic circuits to achieve the minimum possible time delay.

Content

Logic Delay

The unit of delay is the value τ = 3RC , which is the delay time of a simple inverter loaded with one input of a similar inverter in the absence of stray capacitance. The dimensionless quantity corresponding to this delay is called the “normalized delay”. Some authors define the base delay as FO4 ( eng. Fan -out 4 ; delay of an inverter controlled by an inverter four times smaller and loaded by an inverter four times larger). The absolute delay is defined as the product of the normalized delay d and τ :

d_{abs}=d\cdot \tau .

{\ displaystyle d_ {abs} = d \ cdot \ tau.}

In microcircuits manufactured in a typical 600-nm technological process, τ is about 50 ps, in the process of 250 nm - 20 ps, in the process of 180 nm - 12 ps, in the process of 45 nm - 4-5 ps.

The normalized delay of the logic circuit can be expressed as the sum of two components: the normalized "spurious delay" p (which is equal to the delay of the unloaded inverter), and the "labor of the logic element" f (which depends on the load):

d=p+f.

{\ displaystyle d = p + f.}

The logical element labor costs are composed of two components: “logical labor costs” g , which are calculated as the ratio of the input capacitance of the considered circuit to the input capacitance of the inverter providing the same output current ( g is a constant for a certain class of circuits and is determined by the circuit topology); and “electrical labor” h , which are the ratio of the load capacitance to the input capacitance of the circuit. It should be noted that logical labor costs, unlike electric ones, do not take into account the load capacity. The logical element labor costs are equal

f=gh.

{\ displaystyle f = gh.}

Then the expression for the normalized delay can be written as

d=p+gh.

{\ displaystyle d = p + gh.}

Calculation of logical labor costs of a single-stage logic circuit

KPOP inverters on the critical path are usually constructed with γ = 2. In other words, the p-channel field effect transistor of a complementary pair becomes twice as wide (and, accordingly, has twice as much capacity) than the n-channel. This is done so that the resistance of their channels (and, therefore, the on and off current) are approximately equal ^[1] ^[2] .

The sizes of all transistors are selected so that the output current of the circuit is equal to the output current of an inverter built from a p-transistor of double and n-transistors of single width.

The output drive of a gate is equal to the minimum - over all possible combinations of inputs - of the output drive of the gate for that input.

The output drive of a gate for a given input is equal to the drive at its output node.

The drive at a node is equal to the sum of the drives of all transistors which are enabled and whose source or drain is in contact with the node in question. A PMOS transistor is enabled when its gate voltage is 0. An NMOS transistor is enabled when its gate voltage is 1.

When the sizes of the elements are selected, the logical labor costs at the output of the circuit are the sum of the widths of all transistors whose sources or drains are connected to the input of the circuit. The logical labor input of each input is the sum of the widths of all transistors whose gates are connected to the same input of the circuit.

Logical labor costs of the circuit as a whole are the ratio of the output logical labor to the sum of the input logical labor.

Multistage Logic

The main advantage of the logical labor input method is that it can be easily extended to multi-stage circuits. The total normalized delay of the path D can be described in terms of the total "labor costs of the path" F and spurious delay of the path P (which is the sum of the spurious delays of each cascade):

D=NF^{1/N}+P.

{\ displaystyle D = NF ^ {1 / N} + P.}

The workloads of the path are expressed in terms of the "logical work of the path" G (the product of the logical work of each element) and the "Electric work of the path" (the ratio of the load of the path to its input capacity).

For paths where each element is loaded with only one element (i.e. the next element of the path),

F=GH.

{\ displaystyle F = GH.}

However, for branching schemes, the “branching labor” b must be taken into account; this is the ratio of the total capacity controlled by the circuit to the capacity of the chain in question:

b={\frac {C_{onpath}+C_{offpath}}{C_{onpath}}}.

{\ displaystyle b = {\ frac {C_ {onpath} + C_ {offpath}} {C_ {onpath}}}.}

This yields a path branching effort B which is the product of the individual stage branching efforts; the total path effort is then

F=GHB

{\ displaystyle F = GHB}

It can be seen that b = 1 for gates driving only one additional gate, fixing B = 1 and causing the formula to reduce to the earlier non-branching version.

Minimum delay

It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage logical efforts are equal. For a given combination of gates and a known load, B , G , and H are all fixed causing F to be fixed; hence the individual gates should be sized such that the individual stage efforts are

f=F^{1/N}

{\ displaystyle f = F ^ {1 / N}}

where N is the number of stages in the circuit.

Examples

Inverter Delay

A CMOS inverter circuit.

By definition, the logical labor input g of the inverter is 1. If the inverter is loaded with the input of the same inverter, then the electric power input h is also 1.

The parasitic delay p of the inverter is also equal to 1 (it can be found using the Elmore model of the inverter delay ).

Therefore, the total normalized delay of the inverter loaded with the input of a similar inverter is

d=gh+p=(1)(1)+1=2.

{\ displaystyle d = gh + p = (1) (1) + 1 = 2.}

Delayed items AND NOT and OR NOT

The logical effort of the two-input AND-NOT element is g = 4/3, since the AND-element with the input capacitance 4 provides the same current as the inverter with the input capacitance 3. Similarly, the logical work of the two-input OR-NOT element is g = 5/3 . Due to less logical workloads, AND-NOT elements are preferable to OR-NOT.

For elements with a large number of inputs, the logical labor costs are as follows:

Logical input labor for static CMOS elements with γ = 2
Item type	one	2	3	four	five	n
	Number of inputs
Inverter	one	-	-	-	-	-
AND NOT	-	${\frac {4}{3}}$ ${\ displaystyle {\ frac {4} {3}}}$	${\frac {5}{3}}$ ${\ displaystyle {\ frac {5} {3}}}$	${\frac {6}{3}}$ ${\ displaystyle {\ frac {6} {3}}}$	${\frac {7}{3}}$ ${\ displaystyle {\ frac {7} {3}}}$	${\frac {n+2}{3}}$ ${\ displaystyle {\ frac {n + 2} {3}}}$
OR NO	-	${\frac {5}{3}}$ ${\ displaystyle {\ frac {5} {3}}}$	${\frac {7}{3}}$ ${\ displaystyle {\ frac {7} {3}}}$	${\frac {9}{3}}$ ${\ displaystyle {\ frac {9} {3}}}$	${\frac {11}{3}}$ ${\ displaystyle {\ frac {11} {3}}}$	${\frac {2n+1}{3}}$ ${\ displaystyle {\ frac {2n + 1} {3}}}$

The normalized spurious delay of the AND-AND and OR-NOT elements is equal to the number of inputs.

Therefore, the normalized delay of the two-input AND-NOT element loaded with the same element (in this case, the electric labor costs are equal to 1) is

d=gh+p=(4/3)(1)+2=10/3,

{\ displaystyle d = gh + p = (4/3) (1) + 2 = 10/3,}

and for a two-input element, OR NOT

d=gh+p=(5/3)(2)+1=13/3.

{\ displaystyle d = gh + p = (5/3) (2) + 1 = 13/3.}

Links

↑ Bakos, Jason D. Fundamentals of VLSI Chip Design (neopr.) (Link not available) . University of South Carolina. Date of treatment March 8, 2011. Archived on November 8, 2011.
↑ Dielen, M. An Optimal CMOS Structure for the Design of a Cell Library / M. Dielen, JFM Theeuwen. - 1987 .-- P. 11.

Sources

Rabai Zh.M., Chandrakasan A., Nikolic B. Digital Integrated Circuits: Design Methodology, 2nd edition: Per. from English - M .: LLC “I.D. Williams ", 2007. - 912 p.: Ill.