Hybrid memory cube

Hybrid Memory Cube ( HMC ) is a promising type of computer random access memory developed in the early 2010s by a consortium of companies consisting of: Samsung , Micron Technology , ARM , Hewlett-Packard , Microsoft , Altera , Xilinx ^[1] .

HMC uses a three-dimensional microassembly of several (from 4 to 8) DRAM-memory chips ^[2] , made using through-silicon interconnect technology ( English through-silicon vias ) and microbump microcontact leads. Compared to classic DRAM (SDRAM) chips, more memory banks are used. The memory controller is integrated into the microassembly as a separate logic chip ^[3] . HMC uses standard memory cells, but its interface is not compatible with DDR2 or DDR3 implementations ^[4] .

The technology received an award in the nomination "for the best new technology" from The Linley Group analysts in 2011 ^{[5] [6]} .

The first version of the HMC 1.0 specification was published in April 2013 ^{[7] [8]} . In accordance with it, the HMC uses channels from 8 or 16 full-duplex differential serial lines, each line operates at a speed of 10, 12.5 or 15 Gbit / s ^[9] . The HMC micro assembly is called a “cube”; several cubes can connect to each other, forming a network up to 8 cubes in size. Some channels are used in such a network for direct communication between cubes. ^[10] A typical 4-channel cube is a micro assembly of 31 × 31 × 3.8 mm in size and has 896 BGA pins ^[11] .

A channel of 16 lines operating at 10 Gb / s has a throughput of 40 GB / s (20 GB / s for reception and 20 GB / s for transmission); cubes with 4 or 8 such channels are planned. The bandwidth efficiency is 33–50% for packets of 32 bytes and 45–85% for packets of 128 bytes ^[2] .

As reported at the HotChips 23 conference in 2011, the first generation of HMC demo cubes, assembled from 4 DRAM memory crystals (50 nm) and one 90-nm logic chip, had a 512 MB capacity and a size of 27 × 27 mm. For power, a voltage of 1.2 V was used, power consumption was 11 W ^[2] .

Altera announced HMC compatibility with its 10th generation programmable chips (Arria 10, Stratix 10). It is possible to use up to 16 transceivers per link ^[12] . The first processor using HMC memory was the Fujitsu Sparc64 XIfx announced in 2014 (used in PRIMEHPC FX100 supercomputers) ^{[13] [14] [15]} .

In November 2014, the second version of the HMC specification ^{[16] [17]} was introduced, later it was updated to version 2.1. In the second version of HMC, the density and throughput are doubled, methods for creating chips from 8 DRAM crystals and one logic chip using 3DI and TSV are proposed; link speeds - 12.5, 15, 25, 28 and 30 Gbit / s; Link width - 4, 8 or 16 pairs, 2 or 4 links per microassembly; the logical protocol has been changed, support for atomic operations has been expanded ^[18] .

The third version of the standard was expected in 2016 ^[19] .