Echelon (processor)

The United States Defense Advanced Research Projects Agency (DARPA) has announced the sponsorship of the Ubiquitous High Performance Computing program, which aims to create a prototype server rack system with 1 petaflops performance and 57 kW power consumption . The competition was attended by Intel , MIT , Sandia National Labs and nVidia . The end of this program is scheduled for 2018.

On November 18, 2010, at Supercomputing 2010 in New Orleans , Louisiana , nVidia chief technology engineer Bill Dally announced the Echelon project as a result of the company's work on the DARPA initiative. The Echelon project was announced as a microprocessor, similar in structural features to the latest nVidia GPUs . Despite the fact that at the time of the announcement, the chip existed only on paper, and the design was checked in a number of simulations, some technological features and plans for development and release were disclosed. Charts, graphs and diagrams were shown that demonstrated the internal structure and characteristics of the processor.

The Echelon microprocessor will consist of 128 stream units, each of which contains eight cores. Each core can independently perform floating point operations, and the main feature is that in one clock cycle one core will be able to perform four double precision floating point operations. At the same time, the latest professional nVidia GPUs at the time of the announcement - Fermi - are capable of performing only one operation per cycle. Thus, 1024 Echelon cores give a theoretical total performance of 10 TFLOPS.

The Echelon microprocessor is capable of performing one floating point operation using only 10 picojoules of energy. For comparison, Fermi use 200 picojoules for such an operation.

Another feature of the chip is its cache memory, which has six levels and is 256 MB. The maximum supported amount of external graphics memory is 256 GB.

It is stated that a future version of CUDA will be used as the Echelon chip programming tool, although support for future versions of OpenCL , OpenMP, and Microsoft DirectCompute is not ruled out.

• Konstantin Khodakovsky. NVIDIA Echelon - 25x performance boost (unspecified) . 3DNews (November 26, 2010). Date of treatment November 26, 2010.
• Accent NVIDIA talked about the Echelon processor with a performance of 10 TFLOPS (neopr.) . iXBT.com (November 18, 2010). Date of treatment November 26, 2010. Archived May 11, 2012.
• Gil Russell. Project Echelon: The Future of NVIDIA's Silicon . Bright Side Of News (November 19, 2010). Date of treatment November 26, 2010. Archived May 11, 2012.