Accelerated Transfer Scheme

The accelerated transfer scheme is a combinational logic circuit that is part of the arithmetic-logic device of most modern computers of microprocessors and microcontrollers .

Designed for parallel formation of carry bits when adding binary numbers in the adder. It is usually constructed in a cascade manner, consists of several accelerated transfer schemes of lower bit depth, usually equal to the natural power of the number 2, but there are single-stage accelerated transfer schemes that generate transfer signals for all bits of the word simultaneously.

The advantage of this scheme is a significant acceleration of arithmetic operations, since time is not required for spreading the transfer sequentially across all bits of a machine word, the disadvantage is increased complexity.

Principle of Operation

Terms:
Carry Lookahead Unit ( CLU ) - Accelerated Transfer Scheme.
Carry Look-ahead Adder ( CLA ) - adder circuit with accelerated carry.
Group propagate ( PG ) - group propagation propagation signal.
Group generate ( GG ) - group transfer generation signal.

When using the accelerated transfer circuit ( LCU ), each single bit of the adder generates a transfer generation signal ( $g_{n}$ ${\ displaystyle g_ {n}}$ $g_{n}$ ) and the propagation propagation signal ( $p_{n}$ ${\ displaystyle p_ {n}}$ $p_n$ )

4-bit circuit

4-bit adder with accelerated transfer circuit.

Single digits of the adder are combined into groups of four single digits in each group. Accelerated Transfer Circuit Generates Transfer Signals $C_{1},C_{2},C_{3},C_{4},$ ${\ displaystyle C_ {1}, C_ {2}, C_ {3}, C_ {4},}$ group transfer generation signal ( GG ) and group transfer propagation signal ( PG ).

Logical expression for transfer in one category:

C_{i+1}=a_{i}\cdot b_{i}+(a_{i}\oplus b_{i})C_{i}=G_{i}+P_{i}\cdot C_{i}

{\ displaystyle C_ {i + 1} = a_ {i} \ cdot b_ {i} + (a_ {i} \ oplus b_ {i}) C_ {i} = G_ {i} + P_ {i} \ cdot C_ {i}}

where

G_{i}=a_{i}\cdot b_{i}

{\ displaystyle G_ {i} = a_ {i} \ cdot b_ {i}}

P_{i}=a_{i}\oplus b_{i}

{\ displaystyle P_ {i} = a_ {i} \ oplus b_ {i}}

Here is the point ( $\cdot$ ${\ displaystyle \ cdot}$ ) means logical AND ( AND ), addition sign (+) - logical OR ( OR) and symbol $\oplus$ ${\ displaystyle \ oplus}$ modulo 2 addition EXCLUSIVE OR ( XOR )

For transfers in four digits:

C_{1}=G_{0}+P_{0}\cdot C_{0}

{\ displaystyle C_ {1} = G_ {0} + P_ {0} \ cdot C_ {0}}

C_{2}=G_{1}+P_{1}\cdot C_{1}

{\ displaystyle C_ {2} = G_ {1} + P_ {1} \ cdot C_ {1}}

C_{3}=G_{2}+P_{2}\cdot C_{2}

{\ displaystyle C_ {3} = G_ {2} + P_ {2} \ cdot C_ {2}}

C_{4}=G_{3}+P_{3}\cdot C_{3}

{\ displaystyle C_ {4} = G_ {3} + P_ {3} \ cdot C_ {3}}

Substituting $C_{1}$ ${\ displaystyle C_ {1}}$ at $C_{2}$ ${\ displaystyle C_ {2}}$ then $C_{2}$ ${\ displaystyle C_ {2}}$ at $C_{3}$ ${\ displaystyle C_ {3}}$ then $C_{3}$ ${\ displaystyle C_ {3}}$ at $C_{4}$ ${\ displaystyle C_ {4}}$ we get the final expressions:

C_{1}=G_{0}+P_{0}\cdot C_{0}

{\ displaystyle C_ {1} = G_ {0} + P_ {0} \ cdot C_ {0}}

C_{2}=G_{1}+G_{0}\cdot P_{1}+C_{0}\cdot P_{0}\cdot P_{1}

{\ displaystyle C_ {2} = G_ {1} + G_ {0} \ cdot P_ {1} + C_ {0} \ cdot P_ {0} \ cdot P_ {1}}

C_{3}=G_{2}+G_{1}\cdot P_{2}+G_{0}\cdot P_{1}\cdot P_{2}+C_{0}\cdot P_{0}\cdot P_{1}\cdot P_{2}

{\ displaystyle C_ {3} = G_ {2} + G_ {1} \ cdot P_ {2} + G_ {0} \ cdot P_ {1} \ cdot P_ {2} + C_ {0} \ cdot P_ {0 } \ cdot P_ {1} \ cdot P_ {2}}

C_{4}=G_{3}+G_{2}\cdot P_{3}+G_{1}\cdot P_{2}\cdot P_{3}+G_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}+C_{0}\cdot P_{0}\cdot P_{1}\cdot P_{2}\cdot P_{3}

{\ displaystyle C_ {4} = G_ {3} + G_ {2} \ cdot P_ {3} + G_ {1} \ cdot P_ {2} \ cdot P_ {3} + G_ {0} \ cdot P_ {1 } \ cdot P_ {2} \ cdot P_ {3} + C_ {0} \ cdot P_ {0} \ cdot P_ {1} \ cdot P_ {2} \ cdot P_ {3}}

The 4-bit accelerated transfer scheme is available in integrated design, for example: SN74182 ( TTL ), MC10179 ( ESL ) and MC14582, 564IP4 ^[1] (made using CMOS technology).

16-bit circuit

A 16-bit adder can be created by combining four 4-bit adders with four accelerated transfer schemes (4-bit CLA Adder), supplemented by the fifth accelerated transfer scheme, which is used to process group transfer generation signals - GG and transfer propagation - PG .

Transmission propagation signals received at the input ( $P G$ ${\ displaystyle PG}$ ) and the signals generated by each of the four circuits ( GG ). Then, the accelerated transfer circuit generates corresponding signals.

Let's pretend that $P_{i}$ ${\ displaystyle P_ {i}}$ these are PG signals and $G_{i}$ ${\ displaystyle G_ {i}}$ is the GG from the ith, then the output bits are set as follows:

C_{4}=G_{0}+P_{0}\cdot C_{0}

{\ displaystyle C_ {4} = G_ {0} + P_ {0} \ cdot C_ {0}}

C_{8}=G_{4}+P_{4}\cdot C_{4}

{\ displaystyle C_ {8} = G_ {4} + P_ {4} \ cdot C_ {4}}

C_{12}=G_{8}+P_{8}\cdot C_{8}

{\ displaystyle C_ {12} = G_ {8} + P_ {8} \ cdot C_ {8}}

C_{16}=G_{12}+P_{12}\cdot C_{12}

{\ displaystyle C_ {16} = G_ {12} + P_ {12} \ cdot C_ {12}}

Substituting $C_{4}$ ${\ displaystyle C_ {4}}$ first in $C_{8}$ ${\ displaystyle C_ {8}}$ then $C_{8}$ ${\ displaystyle C_ {8}}$ at $C_{12}$ ${\ displaystyle C_ {12}}$ then $C_{12}$ ${\ displaystyle C_ {12}}$ at $C_{16}$ ${\ displaystyle C_ {16}}$ we get the following expression:

C_{4}=G_{0}+P_{0}\cdot C_{0}

{\ displaystyle C_ {4} = G_ {0} + P_ {0} \ cdot C_ {0}}

C_{8}=G_{4}+G_{0}\cdot P_{4}+C_{0}\cdot P_{0}\cdot P_{4}

{\ displaystyle C_ {8} = G_ {4} + G_ {0} \ cdot P_ {4} + C_ {0} \ cdot P_ {0} \ cdot P_ {4}}

C_{12}=G_{8}+G_{4}\cdot P_{8}+G_{0}\cdot P_{4}\cdot P_{8}+C_{0}\cdot P_{0}\cdot P_{4}\cdot P_{8}

{\ displaystyle C_ {12} = G_ {8} + G_ {4} \ cdot P_ {8} + G_ {0} \ cdot P_ {4} \ cdot P_ {8} + C_ {0} \ cdot P_ {0 } \ cdot P_ {4} \ cdot P_ {8}}

C_{16}=G_{12}+G_{8}\cdot P_{12}+G_{4}\cdot P_{8}\cdot P_{12}+G_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}+C_{0}\cdot P_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}

{\ displaystyle C_ {16} = G_ {12} + G_ {8} \ cdot P_ {12} + G_ {4} \ cdot P_ {8} \ cdot P_ {12} + G_ {0} \ cdot P_ {4 } \ cdot P_ {8} \ cdot P_ {12} + C_ {0} \ cdot P_ {0} \ cdot P_ {4} \ cdot P_ {8} \ cdot P_ {12}}

$C_{4}$ ${\ displaystyle C_ {4}}$ accordingly generates a carry bit to the input of the second circuit; $C_{8}$ ${\ displaystyle C_ {8}}$ at the entrance of the third; $C{12}$ ${\ displaystyle C {12}}$ at the entrance of the fourth; and $C_{16}$ ${\ displaystyle C_ {16}}$ generates an overflow bit.

In addition, you can specify transfer propagation and transfer generation signals for the accelerated transfer scheme:

P_{LCU}=P_{0}\cdot P_{4}\cdot P_{8}\cdot P_{12}

{\ displaystyle P_ {LCU} = P_ {0} \ cdot P_ {4} \ cdot P_ {8} \ cdot P_ {12}}

G_{LCU}=G_{12}+G_{8}\cdot P_{12}+G_{4}\cdot P_{12}\cdot P_{8}+G_{0}\cdot P_{12}\cdot P_{8}\cdot P_{4}

{\ displaystyle G_ {LCU} = G_ {12} + G_ {8} \ cdot P_ {12} + G_ {4} \ cdot P_ {12} \ cdot P_ {8} + G_ {0} \ cdot P_ {12 } \ cdot P_ {8} \ cdot P_ {4}}

16-bit adder with accelerated transfer circuit.

64-bit circuit

Combining the four adder circuits and the accelerated transfer circuit together, we get a 16-bit adder. Four of these blocks can be combined into a 64-bit adder. Additional accelerated transfer schemes (second level) are needed to receive transport propagation signals ( $P_{LCU}$ ${\ displaystyle P_ {LCU}}$ ) and transfer generation signals ( $G_{LCU}$ ${\ displaystyle G_ {LCU}}$ ) from each adder circuit.

64-bit adder with accelerated transfer scheme of the second level.

Strengths and weaknesses

Advantages:

High speed.

Disadvantages:

Higher equipment costs

Parallel transfer generation schemes have a significant speed advantage over sequential transfer schemes .

Literature

Titz U., Schenk K. Chapter 19. Combinational logic circuits. 19.5 Adders. 19.5.3. Adapters with parallel transfer // Semiconductor circuitry = Halbleiter-Schaltungstechnik / Per. with him. G. Karabashev. - Dodeka XXI, 2008 .-- 1784 p. - (Circuitry). - 3000 copies. - ISBN 978-5-94120-200-3 , 978-5-94120-201-0, 3-540-42849-6.

Links

↑ Handbook of Low Frequency Digital CMOS ICs. IP4 - accelerated transfer scheme 564IP4 = MC14582A http://www.rlocman.ru/comp/koz/cd/cdh39.htm

Sources

[1] Handbook of Low Frequency Digital CMOS ICs. IP4 - accelerated transfer scheme 564IP4 = MC14582A http://www.rlocman.ru/comp/koz/cd/cdh39.htm