HyperTransport

HyperTransport operates at frequencies from 200 MHz to 3.2 GHz (for the PCI bus - 33 and 66 MHz). In addition, it uses DDR, which means that data is sent both on the edge and on the slice of the synchronization signal, which allows up to 5200 million sendings per second at a synchronization signal frequency of 2.6 GHz; The frequency of the synchronization signal is adjusted automatically.

HyperTransport supports automatic detection of bus widths from 2 to 32 bits. A full-sized, full-speed 32-bit bi-directional bus is capable of delivering bandwidths up to 51,200 MB / s = 2 (DDR) × 2 × 32/8 (bytes) × 3200 (MHz) (maximum in one direction - 25,600 MB / s) , Being, thus, the fastest tire among their own kind. The bus can be used both in subsystems with high bandwidth requirements ( RAM and CPU ), and in subsystems with low requirements (peripherals). This technology is also able to provide low latency for other applications in other subsystems.

The HyperTransport bus is packet based. Each packet consists of 32-bit words, regardless of the physical width of the bus (the number of data lines). The first word in the package is always the control word. If the packet contains an address, then the last 8 bits of the control word are concatenated with the next 32-bit word, resulting in a 40-bit address. The bus supports 64-bit addressing - in this case, the packet starts with a special 32-bit control word that indicates 64-bit addressing and contains the address bits 40 to 63 (the address bits are numbered starting from 0). The remaining 32-bit packet words contain directly transmitted data. Data is always transmitted in 32-bit words, regardless of their actual length (for example, in response to a request to read one byte on the bus, a packet containing 32 bits of data and a flag indicating that only 8 of these 32 bits are significant )

HyperTransport packets are transmitted on the bus sequentially. An increase in throughput entails an increase in tire width. HyperTransport can be used to transmit system service messages, to send interrupts, to configure devices connected to the bus, and to transfer data.

There are two types of write operations on the bus - posted and non-posted . A written-write operation consists in transmitting a single packet containing the address to which it is necessary to record, and data. This operation is usually used to exchange data with high-speed devices, for example, for DMA transmission. A non-posted write operation consists of sending two packets: the device initiating the write operation sends a packet containing the address and data to the destination device. The destination device, having received such a packet, performs a write operation and sends a packet to the initiating device containing information about whether the recording was successful. Thus, a posted entry allows you to get the maximum data transfer rate (there is no cost for sending a confirmation packet), and a non-posted record allows you to ensure reliable data transfer (the arrival of a confirmation packet ensures that the data reaches the destination).

The HyperTransport bus supports energy-saving technologies, namely ACPI . This means that when the state of the processor (C-state) changes to energy-saving, the state of the devices (D-state) also changes. For example, when you turn off the processor, hard drives are also turned off.

HyperTransport / LDT electrical interface - 1.2 V low - voltage differential signals

CPU Bus Replacement

The HyperTransport bus is widely used, mainly as a replacement for the processor bus. For example, devices with a PCI bus cannot be directly connected to the Pentium processor , since this processor uses its own specialized bus (which may be different for different generations of processors). To connect additional devices (for example, with a PCI bus) in such systems, additional devices are needed to interface the processor bus with the peripheral bus (bridges). These adapters are typically included in specialized chipsets called the Northbridge and Southbridge .

Processors from different manufacturers can use different buses, which means they need different bridges to connect the processor bus to the peripheral buses. Computers using the HyperTransport bus are more versatile and simple, as well as more productive. Once developed, the PCI-HyperTransport bridge allows any processor that supports the HyperTransport bus to communicate with any PCI bus device. For example, the NVIDIA nForce chipset uses the HyperTransport bus to connect between the north and south bridges.

Interprocessor bus

Another application of HyperTransport is the NUMA bus of multiprocessor computers. AMD uses HyperTransport as part of the proprietary Direct Connect Architecture architecture in its line of Opteron , Athlon 64, and Phenom processors . Newusys Horus Bus Connection Technology expands the concept to the level of cluster systems.

Application in routers and switches

HyperTransport can also be used in routers and switches . Switches and routers can have many ports, the data between which should be transmitted as quickly as possible. For example, a 4-port 100-Mbps Ethernet switch needs an internal bus with a bandwidth of at least 800 Mbps (100 Mbps × 4 ports × 2 directions) . HyperTransport bus bandwidth significantly exceeds 800 Mbps, which allows you to use it to build such a switch.

HTX and coprocessor connections

The insufficient bandwidth of the bus connecting the CPU and the coprocessor is often the cause of headaches for computer system developers. The characteristics of HyperTransport allow it to be used for this application, a connector was developed for connecting coprocessors via the HyperTransport bus, called HTX ( eng.HyperTransport eXpansion ), and uses a connector that is mechanically compatible with the one used to connect 16x PCI Express devices. Using the HTX connector allows the expansion card installed in it to directly exchange data with the CPU, as well as to carry out DMA sessions of access to system RAM . Soon, FPGA- based coprocessors will also receive the HyperTransport interface and, thus, the ability to easily integrate with the motherboard. The current generation of FPGAs from major manufacturers ( Altera and Xilinx ) may receive direct support for the HyperTransport interface in the near future.

HyperTransport Consortium

HyperTransport consortium includes companies such as Advanced Micro Devices ( AMD ), Alliance Semiconductor , Apple Computer , Broadcom Corporation , Cisco Systems , NVIDIA , PMC-Sierra , Sun Microsystems , and Transmeta . He manages the HyperTransport specifications, conducts new developments and promotes the standard. For 2005, David Rich of AMD was president of the consortium, Mario Cavalli was general manager, Brian Holden of PMC-Sierra was also vice president and technical development team, and Harry Hirschman Harry Hirschman ) of PathScale led the marketing team.

• OpenCores ht_tunnel (under the MPL license)
• ATI Radeon Xpress 200 for AMD processors
• NVIDIA nForce Professional MCPs
• ServerWorks HT-2000 System Controller
• HyperTransport Bus Used on Apple PowerPC G5 Computers

• Quickpath interconnect
• Front side bus
• PCI Express
• RapidIO
• Fiber channel

• HyperTransport Consortium