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Asynchronous logic

Asynchronous logic is a type of interaction of logical elements of digital devices . It differs from synchronous in that its elements act asynchronously , not obeying the global clock .

Content

  • 1 Description
  • 2 General remarks
  • 3 Models and classification of asynchronous circuits
  • 4 Strong (AND) and weak (OR) conditioning
  • 5 Connection theorem for semimodular schemes
  • 6 Two-wire communication line
  • 7 Asynchronous primitives
    • 7.1 Buffer register
    • 7.2 David Cell
    • 7.3 Re-entry Scheme
    • 7.4 Counting Trigger
  • 8 Design Methodologies
    • 8.1 Petri nets
      • 8.1.1 Signal Graphs
    • 8.2 Change Charts
    • 8.3 Conditional logical networks
    • 8.4 NCL approach
  • 9 Key facts and results
  • 10 Bibliography
  • 11 Further reading
    • 11.1 Reports and books
    • 11.2 Articles
    • 11.3 Patents

Description

Asynchronous circuits are controlled by two signals: a request that is issued after setting the inputs and a response . Relative to the pair of these signals, the transient in the asynchronous circuit is modeled by a delay element , the magnitude of which is finite and unknown in advance. In synchronous circuits, anomalies in dynamic behavior (competition and risk) are masked using a clock. To combat anomalies in asynchronous circuits, an indication mechanism [1] is used , which records the moments of the end of transient processes. The readiness of the indication signals is determined by the values ​​of the real delays, which can vary and depend on the operating conditions of the circuit (for example, temperature). Physically, the indicator of the end of transients in the circuit may be absent, then its role is played by special self-synchronous codes [2] [3] . Thus, in comparison with synchronous circuits, asynchronous in general, contain more logic elements. The main advantages of asynchronous circuits compared to synchronous ones are [4] [5] :

  • stable operation - no failures under any possible operating conditions;
  • Safe operation - stopping at the moment of a malfunction of any element;
  • the absence of periods of downtime in anticipation of the next sync pulse.

Synchronous circuits of almost any level of complexity can be implemented on relatively cheap FPGAs . On the contrary, strictly self-synchronous circuits impose very stringent requirements on the internal structure of FPGAs [6] [7] and practically the only solution is to manufacture FPGAs on order [8] [9] [10] . However, it is worth noting attempts to implement asynchronous circuits on bipolar ROMs [11] [12] , standard PAL (CPLD) [13] [14] and FPGA [15] [16] [17] . Since standard FPGAs are synchronous devices, it is relatively easy to construct matched delay circuits [18] [19] [20] and, more complicated, locally synchronous (GALS) circuits [21] . Most standard FPGAs lack the means to implement arbitrators. One way to circumvent this limitation is presented in [15] . In article [16], to implement a strictly self-synchronous circuit, it is proposed to modify the Atmel AT40K FPGA with a very small unit cell size (fine grained) [22] [23] .

General comments

 
A variant of a countable trigger [24] with a different external environment, which corresponds to a distribution and sequential STG.
  • When designing digital devices, it is customary to functionally separate the operating and control units. The operating unit is responsible for processing data (data path [25] [26] ) and receives commands from the control unit (control path). In many respects, this separation is rather arbitrary [4] . Some devices, for example, an asynchronous bus, a ring interface, an arbiter with a hierarchical structure, and a counter modulo n practically do not process data, but have a complex control algorithm. Other devices, such as an asynchronous register bank or parallel n-bit ALU, are designed for intensive data processing, but their management is quite simple.
  • Asynchronous circuits, like any circuits with memory, require setting initial conditions. In practice, this is accomplished by applying a short reset pulse of the corresponding polarity to the storage elements. See [27] for more details.
  • For the correct operation of asynchronous circuits, it is necessary to set the behavior of the external environment. A scheme that is non-distributive for one external environment may turn out to be distributive for another, consistent for the third, and not half-modular for the fourth.

Models and Classification of Asynchronous Circuits

 
G-triggers on the majority elements [28] [29] (a) two-input G-trigger (C-element), (b) three-input G-trigger.
 
Speed-independent schemes [30] and their STGs: (a) non-semimodular [31] , (b) distribution, (c) non-distribution [32] .

An asynchronous circuit can be considered as a hardware implementation of a parallel distributed program [4] . To run such a program in time, some mechanism is usually needed, while an asynchronous circuit does not need this mechanism. Analogs of operators and commands in an asynchronous circuit are logic elements, triggers, or complex hierarchical modules. The role of the data exchanged by the circuit elements is played by signal switching. Thus, all the events in the level scheme are ordered in time through causal relationships. The order established by the developer must be stored in the circuit, that is, actually generated, which ultimately ensures the correct functioning. In the general case, the classification of self-synchronous circuits is rather complicated and ambiguous [1] [33] . However, there are at least two fairly general models of such circuits with different assumptions about the delay in elements, wires and their connections [34] [35] :

  1. A model with a limited delay (Huffman model, Huffman model [36] ), in which the maximum propagation delay of the signals in the circuit is assumed (worst case). To build such schemes, you need to introduce a delay in the feedback circuit or use local synchronization. Thus, circuits constructed in accordance with the Huffman model are not strictly self-synchronous. An example of the use of the Huffman model is the various micropipelines with matched delay [37] [38] [39] [40] . In general, non-Huffman models are models that use dynamic specification languages ​​for formal analysis or synthesis. Operating devices are thus hard to imagine.
  2. A model with unlimited delay to the branch point ( Muller model [41] [42] [43] ), in which it is assumed that the difference in the delay of the wires after branching is less than the minimum element delay. Schemes built in accordance with the Muller model are divided into several classes:
    • speed-independent circuits ( speed-independent, SI circuits );
    • semi-modular or / and distributive schemes;
    • quasi-delay-insensitive, QDI circuits circuits .

Distribution schemes are a subset of semi-modular, which, in turn, are a subset of SI schemes. In practice, the class of SI circuits is equivalent to the class of QDI. The theory and design methods of QDI schemes are well developed and, therefore, such schemes are most popular for implementation.

Complex asynchronous systems cannot be unambiguously represented by either the Huffman model or the Muller model. Such systems can be constructed as asynchronous state machines [44] [45] or, on a very large scale, as asynchronous microprocessor sets [46] [47] using microprogram control [48] [49] [50] [51] . Similar sets are represented by the series K587 [52] [53] , K588 [54] and K1883 (U83x in the GDR ) [55] . It is advisable to begin training in the design of complex sequential self-synchronous circuits by implementing a simple single-bit processor MC14500B and combining such processors into a computing structure [56] .

Strong (AND) and weak (OR) conditioning

 
Timing chart of an inclusive OR element.
 
The semi-modular scheme of the “including OR” element and its STG synthesized in [1] .

On an intuitive level, conditionality (causal relationship, causality) in asynchronous circuits is the dependence of the order of appearance of the output signals on the order of appearance of the input. This dependence can be strong (AND) and weak (OR), which corresponds to schemes with full indication and early evaluation (early evaluation) [57] .

Suppose a certain event has two reasons:xone {\ displaystyle x_ {1}}   andx2 {\ displaystyle x_ {2}}   . I-conditionality suggests that both eventsxone {\ displaystyle x_ {1}}   andx2 {\ displaystyle x_ {2}}   must take place before an event can occury {\ displaystyle y}   . Thus, in the case of And, each cause strongly precedes the result. An analogue of this behavior in sociology is collectivism and camaraderie. In the case of OR conditionality, the eventz {\ displaystyle z}   can happen after any of the eventsxone {\ displaystyle x_ {1}}   orx2 {\ displaystyle x_ {2}}   happened (healthy individualism).

Thus, in the case of OR, the result appears if at least one event from a set of weak causes has occurred. To determine how the event behavesz {\ displaystyle z}   after both of his weak reasonsxone {\ displaystyle x_ {1}}   andx2 {\ displaystyle x_ {2}}   occurred, the concepts of joint and incompatible conditionality are introduced [58] [59] (respectively, managed and uncontrolled individualism). For two input signals, I-conditionality is modeled using a hysteresis trigger (G-trigger, Muller C-element ) defined by the equationyn=xone⋅x2+(xone+x2)⋅yn-one {\ displaystyle y_ {n} = x_ {1} \ cdot x_ {2} + (x_ {1} + x_ {2}) \ cdot y_ {n-1}}   . A collaborative OR conditionality model is an inclusive OR (EDLINCOR) element [60] that uses an outputyn {\ displaystyle y_ {n}}   hysteresis trigger and is given by the equationzn=xone⋅x2+(xone+x2)⋅yn¯ {\ displaystyle z_ {n} = x_ {1} \ cdot x_ {2} + (x_ {1} + x_ {2}) \ cdot {\ overline {y_ {n}}}}   . The completely incompatible OR conditionality model is arbiter based schemes.

Consider an asynchronous circuit in which there is a two-input OR element (two-input AND element). In the blanking phase, code 00 is set at the input of the OR element, and code 11 is set at the input of the AND element. In the working phase, the inputs will switch to 1 (0) one after the other. It is necessary to indicate both of these changes, but in the case of OR conditionality, the process will develop along one input, and then the second input will be displayed somewhere. In other words, the process begins to branch according to the first input change, without waiting for the second, i.e. without synchronization with the second signal. The more such elements, the greater the parallelism in the circuit. Input synchronization is possible, but undesirable, as it will be a different process with less parallelism.

There are two main methods for modeling OR conditioning on Petri nets (or STGs). One way is to avoid the explicit representation of parallelism at the level of transitions of the Petri net to the level of the so-called interleaving semantics (i.e., with the choice on the traces) - while preserving 1-safety of the Petri net. Another way is to preserve the explicit representation of parallelism, but the Petri net becomes not 1-safe [59] . Thus, OR conditionality is described either as an unsafe but stable Petri net, or as safe but unstable.

Both types of conditionality lead to semi-modular schemes. However, in the case of I-conditionality, these schemes are distributive, and in the case of OR - non-distributive. Distribution schemes can be built from elements of only one type (for example, AND-NOT or OR-NOT), and non-distribution schemes require the use of both types of elements. In the case of an unsafe but stable Petri net, it is also necessary to combat the accumulation of points at the vertices of the OR-causality. The DIMS and NCL methodologies, like any other methodologies with a full indication, have all the advantages and disadvantages of I-conditionality. The graphs of signal transitions in their simplest form also implement a full indication. Change charts allow you to model both AND- and collaborative OR-conditioning, but cannot directly represent processes with conflicts or choices.

Connection theorem for semimodular circuits

Let the circuitA {\ displaystyle A}   andB {\ displaystyle B}   semi-modular with respect to statesa {\ displaystyle a}   andb {\ displaystyle b}   accordingly, whilei {\ displaystyle i}   is the output of the inverter circuitB {\ displaystyle B}   . Open the knotj {\ displaystyle j}   schemeA {\ displaystyle A}   so that an input is formedjone {\ displaystyle j_ {1}}   and exitj0 {\ displaystyle j_ {0}}   . Suppose that among the states in which circuits can goA {\ displaystyle A}   andB {\ displaystyle B}   ofa {\ displaystyle a}   andb {\ displaystyle b}   there are sucha′ {\ displaystyle a '}   andb′ {\ displaystyle b '}   in which the value of the signal at the input and output of the inverter coincides withjone {\ displaystyle j_ {1}}   and withj0 {\ displaystyle j_ {0}}   respectively. Remove from the schemeB {\ displaystyle B}   inverter so that input is formedione {\ displaystyle i_ {1}}   and exiti0 {\ displaystyle i_ {0}}   . Connecti0 {\ displaystyle i_ {0}}   fromjone {\ displaystyle j_ {1}}   andj0 {\ displaystyle j_ {0}}   fromione {\ displaystyle i_ {1}}   . It can be argued that the resulting circuit is semi-modular with respect to the state[a′,b′] {\ displaystyle [a ', b']}   . An intuitive proof of the theorem is given in [1] . A rigorous mathematical proof can be found in [30] . It is important to note that the connection of two circuits by the theorem requires the fulfillment of two conditions: 1) one of the circuits must have an inverter and 2) the presence of statesa′ {\ displaystyle a '}   andb′ {\ displaystyle b '}   . These conditions are not always satisfied and, therefore, not any semi-modular schemes can be combined into one. A generalization of the theorem for milder conditions is given in [2] . A special case of using the theorem is to increase the speed of counters with sequential transfer [61] [62] [63] [64] . In the general case, the application of the theorem gives a qualitatively new scheme of known components, for example, pipeline on G-triggers + static trigger = asynchronous shift register.

Two-wire communication line

Simple synchronous circuits can be interconnected with virtually no problems. If there are no critical signal races in the resulting complex circuit, it will be operational. The connection of asynchronous circuits is much more complicated; in the resulting complex circuit, the asynchrony property may be lost. The result of this will be a shutdown or vice versa, the generation of a burst of pulses. If you do not consider the common wire, then the clock signal to the synchronous circuit is fed through one wire. Asynchronous circuits can also be connected via a single wire [65], but for this you need to use a special sequential self-synchronous code. Compared to the parallel code, this means lower performance and additional hardware costs. To improve performance, you can imagine a spacer as the third signal level [66] [67] . It also allows to reduce the number of wires (if there are no more than two metallization layers), but it does not allow switching lines from different controllers to different performers, that is, it is not suitable for bus structures. Since modern technologies use 7-14 layers of metallization, saving in this way on wires does not make sense. Two wires allow the use of a paraphase [68] [69] [70] communication protocol. For the first time, such an approach was used by D. E. Muller to construct a strictly self-synchronous micro-conveyor [69] . Close to this method is Delay Insensitive Minterm Synthesis (DIMS) [71] . The Null Convention Logic (NCL) methodology [72] is also designed to synthesize strictly self-synchronous micropipelines. Unlike DIMS, where C-elements are used, the NCL uses multi-input G-triggers, which are called threshold elements and the self-synchronous M-of-N code. In some cases, this allows you to build simpler schemes. Note that due to the use of G-flip-flops, the DIMS and NCL micro conveyors realize only I-conditionality [73] . Some methods for constructing micro-conveyors with OR conditionality were considered in [74] [75] . Strictly self-synchronous micro-conveyor circuits can also be synthesized when compiling programs from high-level languages. However, it should be expected that the schemes thus obtained will not be optimal. For example, the adder synthesized in [76] is more complicated than that proposed in [77] .

Asynchronous Primitives

The idea of ​​using primitives to build an asynchronous circuit is similar to the idea of ​​a constructor. Details of such a constructor should be as universal as possible [4] . As a rule, they are described by fragments of stable and safe Petri nets [78] [43] . The most famous asynchronous primitives are:

Buffer Register

 
Ring pulse distributor on WCHB [1] and its STG.

It was first proposed in [69] under the name double-line delay (see also [70] [1] ) and is best known as weak condition half buffer, WCHB [79] .

David Cell

 
The distributor on the cells of David [1] [2] and its STG.

It was named after the French engineer René David who first proposed it [80] . The transistor implementation of the cell is called one place buffer , its generalizations are considered in [1] [2] [3] [48] [81] [82] [83] .

Re-entry scheme

 
The distributor is on the version of D-element [84] and its STG. The scheme has wider possibilities [85] .

It was first proposed in [1] and improved in [2] . The latter version is considered in [3] and is known as multiple use circuit , D-element , Q-element [86] [87] and S-element [29] [88] .

Counting Trigger

 
A variant of the counting trigger [89] [90] [91] [92] with the indicator and its STG.
 
A counting trigger with an indicator built on a JK-trigger [93] and its STG.

Also called toggle, it is a frequency divider into two, which ensures the completion of transients. Early versions of toggle built on elements with inverted inputs are given in [30] [94] [95] [96] . The transition diagram of the circuit [94] is shown in Fig. 5.31 in [2] . The delay of the input inverters in all these circuits is assumed to be zero, and either the XOR element or the XNOR element serves as an indicator. The toggle variant using the dual logical elements 1I-2OR-NOT and 1OR-2I-NOT is given in [97] . Note that such an implementation has been known since at least 1971 [98] . Другой вариант toggle, использующий те же элементы и два инвертора предложен в [99] и подробно обсуждается в [100] . Реализация toggle только на элементах И-НЕ (ИЛИ-НЕ) [1] [2] иногда называется гарвардский триггер и известна по крайней мере с 1964 года [101] . Компактные статические схемы гарвардского триггера на КМОП транзисторах приведены в [102] [103] , a схема с нагрузочными резисторами - в [104] . Динамическая схема счётного триггера, где предыдущее состояние хранится на емкостях приведена в [105] . Заметим, что большинство счётных триггеров представляют собой последовательностные схемы и поэтому могут быть реализованы только на элементах 2И-НЕ. Существуют, однако, дистрибутивные схемы счётного триггера. Например, в [106] описывается дистрибутивная и очевидно громоздкая схема на четырёх логических и двух С-элементах. Более удачным примером является дистрибутивная схема JK-триггера на 2И-НЕ. Объединив входы J и K, получим счётный триггер.

Последовательное соединение счётных триггеров даёт многоразрядный счетчик, в котором количество срабатываний разрядаi {\ displaystyle i}   вдвое меньше, чем количество срабатываний разряда i-one{\displaystyle i-1}   . Чтобы обеспечить в таких счетчиках независимость от задержек обычно используется индикатор завершения переходных процессов во всех разрядах [1] . Схема конвейерного счетчика впервые предожена в [1] , запатентована в [107] и перепечатана в [2] . Спецификации и схемы счётчиков с постоянным временем ответа приведены в [108] [109] [97] . Также, в [97] приводится последовательный счётчик с задержкой распространения переносов. В [110] предложен программируемый счётчик, в котором взаимодействие с внешней средой осуществляется через последний разряд. За счёт этого достигается постоянное время реакции между запросом к счётчику и ответом. Тот ответ, который получен после N запросов является сигналом с частотой поделённой на N.

Методологии проектирования

When designing an asynchronous circuit, it is necessary to make an assumption of delays. The self-synchronization methodology uses the Muller hypothesis regarding delays in the wires - the entire delay of the wire is given to the output of the element, and the spread of delays in the wires after branching can be neglected. In this case, the wires are generally excluded from consideration. Violation of the Muller hypothesis leads to a violation of the causation of behavior, which is the logical basis of self-synchronization. Causation requires that each event in the system be the cause of at least one other event (the property of displayability of self-synchronous systems [2] ). In logical structures, unlike transmission systems, a change in the state of a piece of wire after branching may not lead to a switching of the logic element and, therefore, may not be indicated. In this case, a piece of wire begins to act as a memory element. To combat this, that is, to construct circuits that do not depend on delays in the wires, it is necessary to use either special switching disciplines (which narrows the class of implemented circuits [111] ), or use special logical or topological constructions, such as isochronous branches [ 112] [113] or field branching (field forks [114] [115] ), requiring the introduction of new hypotheses and / or design techniques that are technology dependent. This problem is compounded with the increasing influence of delays in the wires and the spread of these delays. The vast majority of modern design methodologies lead to schemes that are quasi-insensitive to delays, that is, to schemes where all the branches are quite short and therefore isochronous [116] [117] . The main task of the synthesis of asynchronous circuits is formulated as follows [118] [119] . Specifies a specification that simulates a real process. Then it is analyzed to identify both beneficial and abnormal properties of the process. Based on the analysis, the original specification is modified to prevent or / and eliminate anomalies. According to a new, modified specification, a circuit is synthesized whose behavior coincides with the original specification. A short list of methods for the analysis and synthesis of asynchronous circuits based on event-type models is given in [120] . The full cycle of using these models in modern development tools is discussed in [121] . Synthesis methods based on compilation of programs from high-level languages, as well as on the theory of traces are considered in [122] [123] [124] .

Petri nets

Stable and safe Petri nets are usually used to model the behavior of logic circuits [43] . However, such networks cannot simulate early receipt of the result, since the triggering of transitions is based on I-conditionality. To describe OR conditioning, a network must be insecure (more than one token in a position). When the behavior of the circuit is specified, it is necessary to transform the Petri net into a diagram of changes (Muller diagram), which is a graph with vertices denoted by a vector of stable and excited outputs of elements. Next, make sure that the resulting diagram is semi-modular. If not, this means that the initial description of the circuit in the form of a Petri net is incomplete and additional events should be introduced. If the change diagram is semi-modular, then one can construct the excitation functions of the elements from the transition diagram. Further, if these functions are in the list of elements of the implementation basis, then everything is in order. If not, then you need to introduce additional variables, and therefore, change the original task so that all the functions of the elements correspond to the functions of the implementation basis. This problem is very complex and its formal solution is far from optimal implementation.

Signal Graphs

 
G-trigger [125] and its STG. Other options are given in [126] [127] [128] .
 
Conveyor distributor [1] [2] and its STG.

Based on Petri nets, transitions in which are marked with signal names. They were first proposed in [129] and described in more detail in two different approaches in [130] and [131] . The most famous are now called English. Signal Transition Graphs, STG [132] .

The simplest STG class - STG / MG corresponds to the class of labeled graphs of Petri nets. These are Petri nets, where each position has a maximum of one input transition and one output transition. In such a graph, a position can only have markers removed from it through a single transition leading from it and a transition that is once allowed can be prohibited only at the actual start, therefore a situation cannot be processed where A or B can occur, but not both . Note that graphically the STG replaces the marked transition with its label, and the positions with one input and one output are omitted. Markers in these omitted positions are simply placed on the corresponding arc. In STG, transition labels contain not only the name of the signal, but also a specific type of transition, increasing ("+") or decreasing ("-").

That way, when the transition markeda+ {\ displaystyle a +}   signala {\ displaystyle a}   switches from 0 to 1; when the transition markeda- {\ displaystyle a-}   signala {\ displaystyle a}   switches from 1 to 0. Transitions on the input signals are also distinguished by underlining. To create STG schemes, one or several restrictions are often required: survivability, reliability, constancy, consistent state assignment, unique state assignment, single-cycle transitions.

An STG is alive if, from every available labeling, each transition can eventually be triggered.

An STG is reliable if no position or arc can ever contain more than one marker.

STG is constant if for all arcs a * → b * (where t * means the transition t + or t-) there are other arcs guaranteeing that b * starts before the opposite transition a *.

The STG has a consistent state assignment if the signal transitions strictly alternate between + and - (i.e., you cannot return to the same state).

An STG has a unique state assignment if no two different STG markings have identical values ​​for all signals.

An STG has single-cycle transitions if each signal name in the STG appears in exactly one rising, one falling transition.

Change Charts

 
Correspondence between transition diagrams (Muller diagrams) (b) and change diagrams (c) for a simple G-trigger diagram (a)
 
The majority voting element implemented as including OR for pairs of events (1,2), (1,3), (2,3). His interpreted Petri net and diagram of changes [133] .

Change Diagrams (CD ) [133] [134] [135] like STGs have nodes marked at transitions and arcs between transitions that define the allowed transition triggering sequences. CDs have three types of arcs: strong precedence, weak precedence and unrelated strong precedence, as well as initial marking, although markers are placed in CD transitions instead of positions. Strong preceding arcs are similar to arcs in STGs and can be considered AND arcs, since a transition cannot be started until all arcs pointing to it are marked with a marker. Arcs of weak precedence are arcs of OR, where a transition can be triggered whenever any transition with an arc of weak precedence to it is marked with a marker. Note that a transition cannot have strong and weak arcs at the same time. When arcs of strong or weak precedence cause a transition to start, on all arcs pointing to this transition, the marker is removed and placed on all arcs that allow the transition to start. Since a transition with arcs of weak precedence leading to it can start earlier than all arcs with markers, arcs without markers have open loops added to them to indicate the “debt” of one marker. When a marker reaches an arc with debt, the marker and debt are mutually destroyed. Thus, if a marker arrives at each input arc of weak precedence to a node (if none of these arcs are initially marked with markers or open loops), it will be launched only once, and can do this as soon as the first marker arrives. Finally, liberated arcs of strong precedence are identical to arcs of strong precedence, except that after the transition leading to the start, the arc no longer holds back the system (considered to be removed from the CD). Thus, these arcs can be used to associate an initial, non-repeating set of transitions with an infinitely repeating cycle.

Conditional Logical Networks

They were first proposed in [58] under the name of English. Causal Logic Nets, CLN with the goal of combining the benefits of Petri nets and change diagrams in representing various forms of causal relationships [59] .

NCL Approach

The abbreviation NCL stands for Null Convention Logic and indicates the use of delimiter 00 . The NCL approach was proposed in [136] for operating units consisting primarily of self-synchronous combinational logic.

Elements of NCL are a special case of a generalized C-element, which is defined using the Shannon decomposition asx=x¯S(x)∨xR¯(x) {\ displaystyle x = {\ overline {x}} S ({\ mathbf {x}}) \ vee x {\ overline {R}} ({\ mathbf {x}})}   whereS(x) {\ displaystyle S ({\ mathbf {x}})}   andR¯(x) {\ displaystyle {\ overline {R}} ({\ mathbf {x}})}   - These are the installation and reset functions. If these functions are orthogonal, i.e.S(x)R(x)=0 {\ displaystyle S ({\ mathbf {x}}) R ({\ mathbf {x}}) = 0}   thenS(x)⩽R¯(x) {\ displaystyle S ({\ mathbf {x}}) \ leqslant {\ overline {R}} ({\ mathbf {x}})}   andx=f(x) {\ displaystyle x = f ({\ mathbf {x}})}   isotone (positive unate) byx {\ displaystyle x}   . In this way,x¯ {\ displaystyle {\ overline {x}}}   can be excluded so thatx=S(x)∨xR¯(x) {\ displaystyle x = S ({\ mathbf {x}}) \ vee x {\ overline {R}} ({\ mathbf {x}})}   . The NCL uses threshold set and reset functions that have a maximum of 4 variables. The NCL also uses 3 non-threshold functions that can be implemented by several NCL elements. NCL + complementary approach uses separator 11 . The setup function for NCL is oneS(x)=xonex2...xn,n⩽four {\ displaystyle S ({\ mathbf {x}}) = x_ {1} x_ {2} ... x_ {n}, n \ leqslant 4}   , and there are several reset functions [137] [138] . For NCL +, vice versa, there is one reset function.R¯(x)=xone∨...∨xn {\ displaystyle {\ overline {R}} ({\ mathbf {x}}) = x_ {1} \ vee ... \ vee x_ ​​{n}}   , and there are several installation functions [139] . The result of this is a certain symmetry between the CMOS implementations of the elements NCL and NCL + [140] .

Note that an approach using, like the NCL, T-triggers of a special type was proposed much earlier in [1] . It has two differences, the first is paraphase circuits and the second is a functionally complete basis. The similarity between the two approaches is the assumption that the basic element circuits are insensitive to delays in the internal wires (DI assumption). This allows you to get closer to the implementation of circuits that are not sensitive to delays in the connecting wires between the elements. However, the CMOS implementation of NCL is very cumbersome, for example, the TH24 element consists of 28 transistors [140] . This may violate the DI assumption, not to mention the 8th AND-OR-NOT input element in the universal module of the earlier approach [141] . Thus, the payment for insensitivity to delays in the wires is extreme redundancy, low speed and insufficient reliability of circuits in the CMOS implementation. We also note that since threshold functions are a subset of monotone, both of the above approaches can be considered as the development of sequential schemes on threshold elements [142] [143] [144] [145] .

Building operational blocks on the NCL is called Flow Computation . These blocks are coupled oscillators that perform parallel computations. A similar principle is used in two-dimensional distributors [146] [147] [148] .

Key Facts and Results

  • Asynchronous circuits can be considered as a generalization of a ring oscillator. That is, if the outputs of the circuit are connected through the model of the external environment with the inputs, the circuit will begin to oscillate.
  • The spacer is present only in two-phase self-synchronous (CC) codes. A single-phase SS code is a code with direct jumps. Other single-phase SS codes do not exist.
  • The implementation of logical functions. So far, the best universal approach is cross-implementation [115] [149] . Any logical function of two or more variables has functional contests, which, in principle, cannot be fought. However, on comparable sets, a monotone (unate) function is free from functional contests. Therefore, we double the number of input variables and replace the inversion of the variable with an independent variable. In order for input sets to become comparable, a two-phase discipline is needed in which each working set is interspersed with a spacer (a separator consisting of either all zeros or all units). Since the spacer is comparable to any working set, we find that in the two-phase sequence of inputs, all adjacent sets are comparable, which is necessary for the absence of functional contests. Logical contests remain (implementation attribute). In this case, cross-implementation helps. A second implementation channel is added that implements the inverse function (the first channel implements the function itself). Moreover, the implementation of this channel should be a dual implementation of the main channel. With this implementation, all pure inverters in each channel are replaced by cross-connections, since each output of an element of a certain tier corresponds to an output of an element in the same tier of the inverse channel. These two outputs form a pair of paraphase code, which greatly facilitates the construction of an indicator for logic. In the case of using two-phase discipline with a spacer, paraphase implementation in CMOS technology does not lead to an increase in the number of transistors compared to clocked single-phase logic. This is due to the fact that in the case of single-phase implementation, CMOS circuits contain direct and inverse channels. An analysis of the redundancy of self-synchronizing codes suggests that for a synchronous combinational circuit withh {\ displaystyle h}   entrances andq {\ displaystyle q}   outputs must have an asynchronous circuit withh+log2(h) {\ displaystyle h + log_ {2} (h)}   entrances andq+log2(q) {\ displaystyle q + log_ {2} (q)}   exits. This assessment corresponds to a hypothetical implementation with minimal additional equipment, that is, in practice, the lower limit is unattainable.
  • Implementation of indicators. Channels for indicating the moments of the end of transients are built on the basis of G-triggers. Since the G-trigger contains the And component, the number of its inputs is limited. Thus, it is necessary to use either pyramids from G-flip-flops, or parallel compression systems, which leads to equipment costs and an increase in the delay in the display circuit, which can drastically reduce performance due to work on real delays. Using the property of two-sided conductivity of a MOS transistor allows constructing a two-stage indicator circuit with an almost unlimited number of inputs and the equipment consumption of 4 transistors per indicated input [150] [151] [149] .
  • Some self-synchronous devices can be implemented with a negligible increase in equipment compared to synchronous implementation. For example, counters (1974) and memory (1986) [152] [153] [154] .
  • Delay-independent circuits (DI [155] , foam-rubber wrapper [156] ), which consist of elements with one output, can contain only inverters and C-elements, which does not allow constructing practical circuits quite flexibly [111] [157] . It is impossible to build a fully independent of delays G-trigger, RS-trigger, T-trigger [115] .
  • Any distribution scheme can be correctly implemented on two-input AND-NOT (OR-NOT) elements with a load capacity of not more than two. Any semi-modular circuit can be correctly implemented only when these elements are used together or when three-input AND-OR-NOT elements are used. The question of the correct implementation of semi-modular circuits only on AND-NOT (OR-NOT) elements remains open [2] [158] [159] . In practice, however, the minimum basis does not make much sense due to the high complexity of the resulting schemes. With an increase in the values ​​of branching coefficients and with an increase in the functional capabilities of the circuit, they become more compact. In modern CMOS technology, it is advisable to use elements whose complexity does not exceed 4I-4OR-NOT. There is no half-modular circuit of AND-NOT elements that is not sensitive to delays in at least two branches of the wire connected to the output of the element for which the states of this circuit are living [160] . If the wire branches, then this is an OR function, so somewhere you need to indicate the signals in the branching wires (OR conditionality). All of the above is true only for a paraphase implementation, a special case of which is the implementation of a C-element only on AND-NOT elements. The question of implementing single-phase distribution schemes on only AND-NOT elements remains open. Однако, в случае однофазного С-элемента нужны элементы обоих типов. Действительно, чтобы реализовать сильную причинность по нарастающим фронтам, нужен элемент И-НЕ, а по спадающим - ИЛИ-НЕ.
  • По одному и тому же проводу запрос можно передавать напряжением, а подтверждение — током. В этом случае для индикации моментов окончания переходных процессов необходимо использовать датчики потребляемого тока КМОП элементов. Однако такие датчики сложны в реализации, а их быстродействие недостаточно. Таким образом, идея комбинированной индикации на практике не ведет к упрощению оборудования. Примером удачного использования этой идеи является метод самосинхронной передачи данных, где каждый бит передается по одному проводу [161] . Для параллельной передачиn {\ displaystyle n}   разрядного двоичного кода этому методу требуется лишь n+2{\displaystyle n+2}   проводов, а его производительность не хуже, чем при передачи данных по двум проводам.
  • Индикаторы завершения переходных процессов могут быть построены на основе пороговых схем с несколькими выходами [162] .

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Further reading

Отчёты и книги

  1. DE Muller, Theory of asynchronous circuits. Report no. 66, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1955.
  2. JC Nelson, Speed-independent counting circuits. Report no. 71, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.
  3. DE Muller, WS Bartky, A theory of asynchronous circuits I. Report no. 75, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.
  4. DE Muller, WS Bartky, A theory of asynchronous circuits II. Report no. 78, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1957.
  5. JH Shelly, The decision and synthesis problems in semimodular switching theory, PhD thesis, University of Illinois at Urbana-Champaign, 1959, 93 p.
  6. WS Bartky, A theory of asynchronous circuits III. Report no. 96, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1960.
  7. AM Bush, A method for sensing the completion of operations in speed-independent asynchronous computer circuits. MSc thesis, Georgia Institute of Technology, 1961, 67 p.
  8. WD Frazer, A switching theory for bilateral nets of threshold elements. PhD thesis, University of Illinois at Urbana-Champaign, 1963, 69 p.
  9. RE Swartwout, Further studies in speed-independent logic for a control. PhD thesis, University of Illinois at Urbana-Champaign, 1962, 104 p.
  10. Р. Миллер, Теория переключательных схем, не зависящих от скорости, Гл. 10 в кн. Теория переключательных схем. Том 2: Последовательностные схемы и машины. Наука, 1971, стр. 242—298.
  11. А. Г. Астановский, В. И. Варшавский, В. Б. Мараховский и др. Апериодические автоматы. М. Наука, 1976, 423 с.
  12. С. Ангер, Схемы вырабатывающие сигналы завершения, § 6.1 в кн. Асинхронные последовательностные схемы, Наука, 1977, 400с.
  13. А. Фридман и П. Менон, Логические элементы с неограниченными задержками, § 4.9 в кн. Теория и проектирование переключательных схем, М. Мир, 1978, стр. 275—282.
  14. CL Seitz, "System timing, " Ch. 7 in Introduction to VLSI Systems, C. A Mead and L. A Conway, pp. 218—262, Addison-Wesley, 1980.
  15. Б. С. Цирлин, Алгебра и анализ асинхронных логических схем. Препринт, Ин-т соц.-экон. пробл. АН СССР, 1981, 39 с. (inaccessible link)
  16. Ю. В. Мамруков, Анализ апериодических схем и асинхронных процессов. Диссертация к.т.н. ЛЭТИ, 1984, 219 с. (inaccessible link)
  17. Н. А. Стародубцев, Синтез схем управления параллельных вычислительных систем. Л. Наука, 1984, 191 с.
  18. В. И. Варшавский, М. А. Кишиневский, В. Б. Мараховский и др. Автоматное управление асинхронными процессами в ЭВМ и дискретных системах. М.: Наука, 1986. Translated to English as Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems.
  19. VI Varshavsky (ed.), Hardware Support of Parallel Asynchronous Processes. Research report, Helsinki University of Technology, 1987, 235 p.
  20. T.-A. Chu, Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. Ph.D. thesis, Massachusetts Institute of Technology, 1987, 189 p.
  21. VI Varshavsky, Circuits insensitive to delays in transistors and wires. Technical report no. 7, Helsinki University of Technology, 1989, 42 p.
  22. L. Lavagno, Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs. PhD thesis, University of California at Berkeley, 1992, 306 p.
  23. О. А. Изосимов. Методы синтеза и динамического анализа самосинхронных КМДП СБИС. Диссертация к.т.н., МИФИ, 1993, 165 с. (inaccessible link)
  24. M. Kishinevsky, A. Kondratyev, A. Taubin and V. Varshavsky, Concurrent Hardware: The Theory and Practice of Self-Timed Design, Wiley, 1993, 388 p.
  25. K. van Berkel, Handshake Circuits: An Asynchronous Architecture for VLSI Programming. Cambridge, 225 p.
  26. JA Brzozowski, C.-JH Seger, Asynchronous Circuits. Springer, 1995, 404 p.
  27. SS Appleton, Performance-directed design of asynchronous VLSI systems. PhD thesis, University of Adelaide, 1997, 285p.
  28. SP Wilcox, Synthesis of asynchronous circuits. PhD dissertation, University of Cambridge, 1999, 250 p.
  29. CJ Myers, Asynchronous Circuit Design. Wiley, 2001, 392 p.
  30. J. Sparsø, "Asynchronous circuit design — a tutorial, " Chapters 1-8 in Principles of asynchronous circuit design: A systems perspective. Kluwer, 2001, 152p. Translated to Russian as «Проектирование асинхронных схем — вводное руководство»
  31. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis for Asynchronous Controllers and Interfaces. Springer, 2002, 272 p.
  32. A. Yakovlev, Theory and Practice of Using Models of Concurrency in Hardware Design. DSc. thesis based on publications, University of Newcastle upon Tyne, 2005, 27 p.
  33. KM Fant, Logically Determined Design: Clockless System Design with NULL Convention Logic. Wiley, 2005, 292 p.
  34. WB Toms, Synthesis of Quasi-Delay-Insensitive Datapath Circuits. PhD thesis, University of Manchester, 2006, 237 p.
  35. PA Beerel, RO Ozdag, M. Ferretti, A Designer's Guide to Asynchronous VLSI. Cambridge, 2010, 339 p.
  36. Л. П. Плеханов, Основы самосинхронных электронных схем. Бином, 2013, 208 с.
  37. В. Б. Мараховский, Л. Я. Розенблюм, А. В. Яковлев. Моделирование параллельных процессов. Сети Петри. СПб., Профессиональная литература, 2014, 400с.

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Источник — https://ru.wikipedia.org/w/index.php?title=Асинхронная_логика&oldid=101893542


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