FRAM

The first information on the use of ferroelectrics in digital storage devices dates back to the 1970s. In the USSR , the copyright certificate 690564 ^{[2] was} published and microcircuits of the ferroelectric memory series 307РВ1 ^{[3] were} issued. However, the difficulties of use, in particular, the need for high voltages, did not allow the technology to be widely used.

The development of modern FeRAM technology began in the late 1980s . In 1991, work was done at the NASA Jet Propulsion Laboratory to improve reading methods, including a new non-destructive reading method using pulses of ultraviolet radiation ^[4] .

Much of the current FeRAM technology was developed by the fabless company Ramtron International , a specialist in the semiconductor industry. One of the main licensees was Fujitsu , which, according to some estimates, has the largest base for the production of semiconductors , including a production line suitable for the production of FeRAM. Since 1999, they have used this line to produce individual FeRAM chips along with specialized chips (e.g. smart card chips) with integrated FeRAM. This fit perfectly with Fujitsu's Ramtron device manufacturing plans.

Since 2001, Texas Instruments has been collaborating with Ramtron in the development of FeRAM test chips for an updated 130 nm process. In the fall of 2005, Ramtron announced that they were able to significantly improve prototypes of 8-megabyte FeRAM chips manufactured using the power of Texas Instruments. In the same year, Fujitsu and Seiko-Epson began cooperation in the development of a 180-nm FeRAM process .

FeRAM research projects have been announced by Samsung , Matsushita , Oki , Toshiba , Infineon , Hynix , Symetrix , University of Cambridge, University of Toronto and Interuniversity Microelectronics Center (IMEC, Belgium ).

Milestones: 1984 - RAMTRON began developing a technology for manufacturing FRAM storage devices.

1989 - The first factory for the production of FRAM was commissioned.

1993 - the first commercial product (FRAM chip with a capacity of 4 Kbit memory launched into serial production).

1996 - production of the 16 Kbit FRAM chip was launched.

1998 - mass production of FRAM using technology with a topological norm of 1.0 microns.

1999 - mass production of FRAM using 0.5-micron technology, FRAM chips with 64 Kbit and 256 Kbit memory.

2000 - production of 1 Mbit FRAM with a 1T1C type cell, the beginning of the production of FRAM microcircuits with a supply voltage of 3 V.

2001 - Introduction of FRAM production technology with a topological norm of 0.35 microns.

Regular DRAM memory consists of a grid with small capacitors and associated contact and signal transistors . Each information storage element consists of one capacitor and one transistor, a similar circuit is also called a 1T-1C device. The dimensions of the DRAM element are directly determined by the dimension of the semiconductor manufacturing process used in their manufacture. For example, according to the 90-nm process used by most memory manufacturers in the production of DDR2 DRAM, the element size is 0.22 μm², which includes a capacitor, transistor, their connection, as well as a certain amount of empty space between the various parts - usually the elements occupy 35% of the space, leaving 65% as empty space.

Data in DRAM is stored in the form of the presence or absence of an electric charge on the capacitor, and the absence of charge is indicated as "0". Recording is done by activating the corresponding control transistor, allowing the charge to “drain” to store “0”, or vice versa, let the charge pass into the cell, which will mean “1”. Reading takes place in a very similar way: the transistor is activated again, the drainage of the charge is analyzed by the read amplifier . If a charge pulse is marked by an amplifier, then the cell contained a charge and thus reads “1”, the absence of such a pulse means “0”. It should be noted that this process is destructive , that is, the cell is read once, if it contained "1", then it must be recharged to continue storing this value. Since the cell loses its charge after some time due to leaks, then, at certain intervals, the regeneration of its contents is required.

The 1T-1C type cell designed for FeRAM is similar in design to both types of cells commonly used in DRAM memory, including a structure consisting of one capacitor and one transistor. A linear dielectric is used in the capacitor of a DRAM cell, while a dielectric structure including a ferroelectric is used in the capacitor of a FeRAM cell, usually lead zirconate titanate piezoelectric ceramic (PZT).

A ferroelectric has a nonlinear coupling between the applied electric field and the stored charge. In particular, the ferroelectric characteristic has the form of a hysteresis loop, which is very similar to the general outline of a hysteresis loop of ferromagnetic materials. The dielectric constant of a ferroelectric, as a rule, is significantly higher than that of a linear dielectric, due to the effect of semi- constant electric dipoles formed in the crystal structure of a ferroelectric material. When an external electric field penetrates through the dielectric, the dipoles are aligned in the direction of the applied field, leading to small displacements of the positions of atoms and displacements of the passage of electric charge in the crystal structure. After the charge is removed, the dipoles retain their polarization state. Typically, binary “0” and “1” are stored as one of two possible electrical polarizations in each data storage cell. For example, “1” means the negative polarization residue “-Pr”, and “0” means the positive polarization residue “+ Pr”.

FeRAM is functionally similar to DRAM. The recording occurs by penetrating the field through the ferroelectric layer when charging the electrodes, forcing the atoms inside to take an orientation up or down (depending on the polarity of the charge), due to which “1” or “0” is stored. However, the principle of reading is different from the implementation in DRAM. The transistor puts the cell in a special state, reporting "0". If the cell already contains "0", then nothing will happen on the output lines. If the cell contained “1”, then the reorientation of the atoms in the interlayer will lead to a short pulse at the output, since they will push the electrons out of the metal on the “lower” side. The presence of this impulse will mean that the cell stores "1". Since the process overwrites the contents of the cell, reading from FeRAM is a destructive process, and requires the regeneration of data in the cell if it changes during reading.

Generally speaking, the functioning of FeRAM is very similar to magnetic core memory - one of the first types of computer memory in the 1960s. In addition, the ferroelectric effect used in FeRAM was discovered in 1920. But now FeRAM requires much less energy to change the state of polarity (direction), and it does this much faster.

Among the advantages of FeRAM over flash memory :

• low power consumption;
• quick record of information;
• significantly increased maximum number (exceeding 10 ¹⁴ for devices rated at 3.3 V) of dubbing cycles.

The disadvantages of FeRAM include:

• much lower density of information ;
• limited storage capacity;
• higher cost.

Flash memory cells can store several bits per cell (currently 3 at a higher density for flash chips like NAND), and it is planned to increase the number of bits per flash cell to 4 or even 8 thanks to new technologies in the field of creating flash cells. The flash bit density range, as a result, is significantly larger than FeRAM, and thus the cost of the flash bit is lower than FeRAM.

Density

The main determining factor in the cost of the memory subsystem is the density of the components. Reducing the components (or their number) means that more cells can fit on one chip, which, in turn, means that more can be produced from one silicon wafer at a time. This increases revenue, which directly affects the cost.

The lower limit in this scaling process is one of the key points of comparison, which is typical for all technologies in general, scalable to the smallest cell sizes and abut this limit, which does not allow them to get cheaper any further. FeRAM and DRAM are similar in design, and can even be produced on similar lines with similar sizes. In both cases, the lower limit is determined by the amount of charge required by the trigger of the read amplifier. For DRAM, this turns into a problem at 55 nm, since at this size the amount of charge stored by the capacitor becomes too small to detect. It is still unknown whether FeRAM can be reduced to a similar size, since the charge density on the PZT layer may not be the same as that of metal electrodes in a conventional capacitor.

An additional size limitation is that the material loses ferroelectric properties with a strong decrease in size ^{[5] [6]} (this effect is associated with the “depolarization field” of the ferroelectric). Currently, research is being conducted on the stabilization of ferroelectric materials; One solution, for example, is the use of molecular adsorbates ^[5] .

Commercial FeRAM solutions are currently manufactured using 350nm and 130nm processes. Early models required dual FeRAM cells to store one bit, which caused very low density, but this limitation was subsequently overcome.

Power Consumption

A key advantage of FeRAM over DRAM is what happens between read and write cycles. In DRAM, the charge located on the metal electrodes flows through the insulating layer and the control transistor, and as a result disappears completely. Also, in DRAM for storing data longer than a few milliseconds, each cell must be periodically read and rewritten, which is called “regeneration”. Each cell must be updated many times per second (~ 65 ms ^[7] ), which requires a constant power source.

In contrast, FeRAM only requires power when it is actually read or written to a cell. A significant part of the energy used by DRAM is spent on regeneration, therefore the measurement results referred to by the TTR-MRAM developers are also quite appropriate here, indicating energy consumption is 99% lower compared to DRAM.

Another type of non-volatile memory is flash memory , which, like FeRAM, does not require a regeneration process. Flash memory works by pushing electrons through a high-quality insulating barrier, where they are trapped at one end of the transistor . This process requires a high voltage, which is provided by the charge pump generator . This means that FeRAM by its device consumes less power than flash memory, at least when writing, since the power consumption for writing to FeRAM is only slightly higher than when reading. For devices, which are mainly characterized by reading, the differences will be completely insignificant, but for devices with a more balanced level of reading / writing, the difference can be much larger.

Performance

DRAM performance is limited by the level at which the current charge stored in the cells can be “drained” (when reading) or “pumped” (when writing). In the general case, this is limited by the capabilities of the control transistors, the capacity of the lines supplying power to the cells, and also the temperature created.

FeRAM is based on the physical movement of atoms when exposed to an external field, which occurs extremely quickly, taking about 1 ns. In theory, this means that FeRAM can be faster than DRAM. However, due to the fact that the power must be supplied to the cell during reading and writing, various delays associated with power supply and switching will reduce performance to a level comparable to DRAM. For this reason, we can say that FeRAM requires a lower charge level than DRAM, since DRAM chips need to hold a charge, while FeRAM will be overwritten before the charge is drained. That is, there is a delay in recording due to the fact that the charge must pass through the control transistor, which imposes its own limitations.

Compared to flash, the benefits are more obvious. While the read operations are similar in performance, the charge pump is used for recording, requiring a considerable amount of time for “tuning”, and a similar process in FeRAM does not require this. Flash memory generally takes about 1 ms to write a bit, while even current FeRAM chips require 100 times less time.

With the theoretical performance of FeRAM, not everything is clear. Existing 350 nm samples have a reading time of about 50-60 ns. Although they are comparable in speed to modern DRAM chips, among which you can find instances with indicators of the order of 2 ns, the common 350 nm DRAM chips work with a reading time of about 35 ns ^[8] , therefore, the FeRAM performance looks comparable with a similar production process.

In 2005, semiconductor sales worldwide totaled $ 235 billion (according to Gartner ), with the flash memory market valued at $ 18.6 billion (according to IC Insights). In 2005, annual sales of Ramtron International , probably the largest supplier of FeRAM memory, amounted to $ 32.7 million.

In 2007, FeRAM chips were manufactured according to 350 nm standards at Fujitsu factories and 130 nm at Texas Instruments factories, while flash memory is manufactured using Samsung semiconductors already with 30 nm technology. Flash memory is currently the dominant technology of non-volatile memory ( NVRAM ), and, most likely, this situation will persist, at least until the end of the decade. Significantly more significant sales of flash memory, comparable to alternative NVRAM chips, provide significantly more research and development.

In the fall of 2008, Ramtron International released the first 1Mbps FM28V100 chip, which marked the beginning of the V-Family.

At the end of July 2009, the company announced the release of a new memory chip FM28V020 of the V-Family family (256 Kbit, logical organization 32Kx8) with a parallel interface and a data bus width of one byte. For packaging, a standard SOIC -28 type case was selected, the operating temperature range is −40 ° C and +85 ° C ^[9] .

In early 2011, Ramtron International introduced a number of chips with serial (FM24W256, FM25W256, 256 Kbps, $ 2.35 per unit in a batch of 10,000 pieces) and parallel (FM16W08, 64 Kbps, $ 1.96; FM18W08, 256 Kbps; $ 3.48 ) interface ^[10] . The new W-Family introduced is characterized by a 25-50% lower current in active mode and a 20-fold reduction in initialization time.

In the summer of 2011, Texas Instruments released a variant of the MSP430 microcontroller with FRAM-memory instead of Flash ^[11] .

In October 2012, Fujitsu Semiconductor Europe (FSEU) introduced the 256 Mbps MB85RC256V chip. Guaranteed data storage duration of 10 years at a temperature of 85 degrees Celsius, the number of read / write cycles 1 trillion ^[12] .

FeRAM continues to occupy an extremely small share of the overall semiconductor market.

The density of FeRAM can be raised by improving the technology of the FeRAM production process and the cell structure, for example, by developing structures of vertical capacitors (similar to DRAM) to reduce the area of ​​influence on the cell. However, reducing the size of the cell may cause the charge storing the data to become too weak to detect. In 2005, Ramtron announced significant sales of FeRAM products in various market sectors, including but not limited to electronic measurement, transportation equipment (such as black boxes , smart airbags ), business and office equipment (such as printers , RAID controllers), measuring instruments, medical equipment, industrial microcontrollers , as well as RFID chips. Other existing NVRAM chips, such as MRAM , can take their place in similar market niches by competing with FeRAM.

Theoretically, it is possible to incorporate FeRAM cells using two additional mask steps in the production of conventional CMOS semiconductors . Flash memory usually requires nine masks. This makes it possible, for example, to integrate FeRAM into microcontrollers , where a simpler process will lower the cost. However, the materials used in the manufacture of FeRAM chips are not widely used in the manufacture of CMOS circuits. Like the PZT ferroelectric layer, the noble materials used in the manufacture of electrodes cause oxidation and mutual damage in CMOS.

• Mram
• nvSRAM
• Racetrack memory
• Phase Transition Memory
• Memristor

• Ugryumov E.P. Chapter 5. Storage devices // Digital circuitry. - 3 ed. - BHV-Petersburg, 2010 .-- 816 p. - ISBN 978-5-9775-0162-0 .

• Future memory technology: FeRAM from the inside - a review article on 3Dnews.ru
• Features of the application of FRAM microcontrollers Texas Instruments // RADIOLOTSMAN magazine, April 2012
• What is FRAM? - FRAM review by Fujitsu
• FeRAM Tutorial - FeRAM Guide from the Department of Electrical and Computer Engineering of the University of Toronto

Resources and Communities

• FRAM (FeRAM) Community Sponsored by Ramtron (China)