Microprocessor MCST R-150 ( 1891VM1 ) of the Russian company MCST from the series MCTS-R based on the SPARC architecture , originally developed in 1985 by Sun Microsystems . Fully software compatible with SPARC V8 architecture. Manufactured since 2001. Silicon wafers are manufactured in Israel at the Tower Semiconductor factory, and ASE [1] (Taiwan) is engaged in the packaging and testing of processors. [one]
It is a single-core system on a chip with built-in first-level caches. To connect processors with each other, with memory modules and I / O devices, the SPARC architecture provides the MBus bus, a high-speed bus that ensures the coherence of the processor's cache memory in multiprocessor structures. The microcircuit was developed according to the technological norms of 0.35 microns using the libraries of standard elements.
The microprocessor R-150 is designed to create a computer for stationary and embedded solutions, and can also be placed in mezzanine microprocessor modules. Used mainly by order of the Ministry of Defense of the Russian Federation .
| Specifications | Meanings | |
|---|---|---|
| one | Technological process | CMOS 0.35 microns |
| 2 | Working frequency | 150 MHz |
| 3 | Word size: | 32/64 |
| four | Level 1 instruction cache | 8 KB (2 way) |
| five | Level 1 data cache | 16 KB (4 way) |
| 6 | Level 2 external cache | 1 MB |
| 7 | Bandwidth communication buses with cache memory level 2 | 1.2 GB / s |
| eight | MBus bus bandwidth | 0.4 GB / s |
| 9 | Crystal area | 100 mm² |
| ten | Number of transistors | 2.8 million |
| eleven | The number of metal layers | four |
| 12 | Enclosure type / number of pins | BGA / 480 |
| 13 | Supply voltage | 3.3 V |
| 14 | Power dissipation | <4 W |
Notes
Sources
- CJSC MCST website