UltraSPARC III (codenamed “Cheetah”) is a microprocessor with SPARC V9 instruction system developed by Sun Microsystems and manufactured by Texas Instruments . It was introduced in 2001 and worked at frequencies from 600 to 900 MHz. In 2004, a new UltraSPARC IV processor was created on its basis. The main developer was Gary Lauterbach.
Content
History
At the Microprocessor Forum in 1997, it was announced that UltraSPARC III would appear in 1999 and that it would compete with Alpha 21264 from DEC and Intel's Itanium (Merced). However, the issue was delayed until 2001. Despite this, he was awarded the Microprocessor Report Award for Best Server / Workstation Processor in 2001 for its multiprocessor performance.
Description
UltraSPARC III is a superscalar microprocessor with in-order execution of instructions. UltraSPARC III was designed for multiprocessing with shared memory. This is achieved through an integrated memory controller and multiprocessor bus.
It takes up to four instructions per cycle from the cache. Decoded instructions are sent to the dispatch unit six at a time. The dispatcher device sends instructions to the appropriate execution units, depending on the type of operation and the availability of free resources. Executive resources include two arithmetic logic devices (ALUs), a reader / writer (load / store unit) and two devices for floating point operations. One of the ALUs can only execute simple integer instructions and load data. Two devices with a floating point are also not equivalent. One can only perform simple operations, such as addition, while the other performs multiplication, division, and square root extraction.
Cache
In UltraSPARC III, the cache is divided into a cache for instructions of 32 KB and a cache for data of 64 KB. Layer 2 cache (L2) has a capacity of 8 MB. It is connected via a special 256-bit bus operating at a frequency of 200 MHz, with a peak bandwidth of 6.4 GB / s. The cache is built on the basis of synchronous static RAM operating at a frequency of up to 200 MHz.
Front Ends
The external interfaces consist of a 128-bit data bus and a 43-bit address bus operating at 150 MHz. The data bus is not used to access memory, but to the memory of other microprocessors and general input / output devices.
Physical structure
UltraSPARC III consists of 16 million transistors, 75% of which are in the cache and tags. Initially, it was manufactured by Texas Instruments using C07a technology (0.18 micron CMOS technology with six-layer aluminum compound). In 2001, it was produced using 0.13 micron technology with aluminum compounds. This made it possible to increase the frequency to 750-900 MHz.
Derivatives
UltraSPARC has been enhanced and had three derivatives.
UltraSPARC III Cu
UltraSPARC III Cu ("Cheetah +") - further development based on UltraSPARC III. This processor worked at higher frequencies: from 1002 to 1200 MHz. The matrix size was 232 mm². The processor was manufactured using 0.18 micron CMOS technology with a 7-layer copper compound by Texas Instruments.
UltraSPARC IIIi +
UltraSPARC IIIi + ("Serrano") is a further development of the UltraSPARC IIIi. It was supposed to launch it in the second half of 2005, but its production was canceled in favor of the new UltraSPARC IV + , UltraSPARC T1 and UltraSPARC T2 processors.