Static timing analysis (IAS) is a method for calculating the time parameters of VLSI , which does not require full-fledged electrical modeling of the circuit operation.
Purpose
In synchronous circuits, data is transferred from one trigger to another through some combination section . The triggers are controlled by a clock synchronization signal, the period of which is determined by the delay in transmitting the signal from the input of the trigger to its output. In such systems, two types of errors are possible:
- hold time violation - violation of the hold time.
- setup time violation - violation of the preset time.
The time at which the output signal arrives can vary for many reasons: the circuit can perform different operations, the ambient temperature or voltage varies, change under the influence of the production process, etc. The main task of the CBA in this case is to verify that, despite for all possible variations, the signal will arrive at the output of the circuit within the specified time frame, which is a condition for error-free operation of the circuit.
Definitions
- The critical path is the signal path from the input to the output of the circuit, which has the greatest delay.
- Signal propagation delay is the time it takes an electrical signal to reach a node in the circuit.
- The maximum allowable signal delay is the maximum signal delay, beyond which it is necessary to increase the duration of the clock period.
- Stock (slack) - the value usually calculated for each node of the circuit, equal to the difference between the maximum permissible and actual signal delay.
See also
- Elmore delay