Semi-adder

The generalized image of the half adder.

Half -accumulator - combinational logic circuit having two inputs and two outputs (two-digit adder, binary adder). The half-adder allows you to calculate the sum of A + B , where A and B are bits (usually) of a binary number, with the result being two bits S and C , where S is the sum bit modulo 2, and C is the carry bit.

There are adders and half adders operating not in binary logic.

It differs from the full adder in that it does not have a carry input from the previous digit. To build a full adder, you must have an additional transfer input from the previous digit, so the full adder has 3 inputs.

The binary full adder is built from two half adders and a logical element 2IL, that is why the considered circuit is called a half adder.

Half- adders are used to build full adders .

History

1939 - George Stibits of Bell Laboratories created the first binary Model K Adder binary on two electromechanical relays ^[1] .
1958 - N. P. Brusentsov built the first electronic ternary computer Setun with the first electronic ternary half-adder at Moscow State University (mekhmat) ^[2] .

Binary half-adder

Standard image of binary half adder to DIN 40900 .

Half-adder, implemented on the elements EXCLUSIVE OR and AND .

A semi-adder implemented on OR elements with inverse inputs and AND .

Binary half-adder can be defined in three ways:

tabular, in the form of truth tables ,
analytical, in the form of formulas ( SDNF ),
graphic, in the form of logic circuits.

Since formulas and schemes can be transformed in accordance with the algebra of logic, then many different formulas and schemes can correspond to one truth table of a binary half-adder. Therefore, the tabular method of determining the binary half adder is the main one.

The binary half-adder generates two binary (two-operand) binary logical functions: this is modulo two , otherwise this function is called EXCLUSIVE OR ( XOR ) - forms the sum S bit and the AND function ( AND ) - forms the carry bit C.

S

	0	one
one	one	0
0	0	one

C

	0	one
one	0	one
0	0	0

or in another form:

x ₀ = A	one	0	one	0
x ₁ = B	one	one	0	0	The name of the action (function)	Function number

S	0	one	one	0	Modulo 2 amount bit	F2,6
C	one	0	0	0	Carry bit	F2,8

Non-zero transfer is formed in the 1st case out of 4.

SDNF modulo 2 amounts:

S=\mathbf {f} (x_{1},x_{0})=({\overline {x_{1}}}\cdot {x_{0}})\vee ({x_{1}}\cdot {\overline {x_{0}}})

{\ displaystyle S = \ mathbf {f} (x_ {1}, x_ {0}) = ({\ overline {x_ {1}}} \ cdot {x_ {0}}) \ vee ({x_ {1} } \ cdot {\ overline {x_ {0}}}}}

SDNF bit carry:

C=\mathbf {f} (x_{1},x_{0})={x_{1}}\cdot {x_{0}}

{\ displaystyle C = \ mathbf {f} (x_ {1}, x_ {0}) = {x_ {1}} \ cdot {x_ {0}}}

Heelometer Stibitsa "Model K Adder"

The Stibitsa demonstration semi-adder “Model K Adder” is used for training purposes and consists of two series-connected galvanic cells, 1.5 Volts each, with a total voltage of 3 Volts, two buttons for entering two bits of arguments A and B , two electromagnetic relays, performing binary binary logic addition function modulo 2 and binary binary logic function of the transfer bit in binary addition, and two incandescent bulbs with a voltage of 3 volts to indicate the amount sum bit modulo 2 ( S ) and the transfer bit ( C ) ^[1]

Threefold half-adder

Since there are two ternary number systems - asymmetric, in which there is no value greater than 1 in the transfer discharge, and symmetric (Fibonacci), in which all three states of trita are possible in the transfer discharge, and at least three physical implementations of ternary systems three-level single-wire, two-level two-wire (BCT) and two-level three-bit single-unit, then there may be a large number of ternary half-adders.

The ternary half-adder in an asymmetric ternary number system is the union of two binary ternary logic functions - “addition modulo 3” and “transfer discharge with ternary addition”.

S

	0	one	2
2	2	0	one
one	one	2	0
0	0	one	2

C

	one	2
2	one	one
one	0	one
0	0	0

or in another form:

x ₁ = x	2	2	2	one	one	one	0	0	0
x ₀ = y	2	one	0	2	one	0	2	one	0	The name of the action (function)	Function number

S	one	0	2	0	2	one	2	one	0	Three times modulo 3
C	one	one	0	one	0	0	0	0	0	Trit Carry

The ternary half-adder in the symmetric ternary number system is also a half-reader and is a combination of two binary ternary logical functions - the “low order (trit) of the difference-sum” and symmetric number system) ".

Threefold half-adder.

S

	-one	0	+1
+1	0	+1	-one
0	-one	0	+1
-one	+1	-one	0

C

	-one	+1
+1	0	+1
0	0	0
-one	-one	0

or in another form:

x ₁ = x	one	one	one	0	0	0	7	7	7
x ₀ = y	one	0	7	one	0	7	one	0	7	The name of the action (function)	Function number

S	7	one	0	one	0	7	0	7	one	Junior trit sums	F710107071 = F-4160
C	one	0	0	0	0	0	0	0	7	Senior trit sums (transfer trit)	F100000007 = F6560

The number "7" here means "-1"

Non-zero transfer is formed in 2 cases out of 9.

A ternary three-level half adder is described in ^[3] .

A three-way two-bit two-wire binary (two-operand) single-bit (BCT) semi-adder operating in an asymmetric ternary number system is given in ^[4] , in the BCT Addition section, in subsection (f) Circuit diagram and, with the erroneous name “two-digit BCT adder,” in ^{[ 5]} in the figure.

The figure on the right shows the scheme of the ternary asymmetric half-adder in a three-bit single-unit system of ternary logic elements described in ^[6] .

The ternary mirror-symmetric single-bit half-adder is described in ^[7] .

Decimal semi-adder

Consists of two tables of size 10x10. The first table is the sums modulo 10, the second table is the units of transfer in binary (two-operand) decimal addition ^[8] .

S

	0	one	2	3	four	five	6	7	eight	9
9	9	0	one	2	3	four	five	6	7	eight
eight	eight	9	0	one	2	3	four	five	6	7
7	7	eight	9	0	one	2	3	four	five	6
6	6	7	eight	9	0	one	2	3	four	five
five	five	6	7	eight	9	0	one	2	3	four
four	four	five	6	7	eight	9	0	one	2	3
3	3	four	five	6	7	eight	9	0	one	2
2	2	3	four	five	6	7	eight	9	0	one
one	one	2	3	four	five	6	7	eight	9	0
0	0	one	2	3	four	five	6	7	eight	9

C

	one	2	3	four	five	6	7	eight	9
9	one	one	one	one	one	one	one	one	one
eight	0	one	one	one	one	one	one	one	one
7	0	0	one	one	one	one	one	one	one
6	0	0	0	one	one	one	one	one	one
five	0	0	0	0	one	one	one	one	one
four	0	0	0	0	0	one	one	one	one
3	0	0	0	0	0	0	one	one	one
2	0	0	0	0	0	0	0	one	one
one	0	0	0	0	0	0	0	0	one
0	0	0	0	0	0	0	0	0	0

Hexadecimal

It consists of two tables measuring 16x16. The first table is the sums modulo 16, the second table is the units of transfer with binary (two-operand) hexadecimal addition.

S

	0	one	2	3	four	five	6	7	eight	9	A	B	C	D	E	F
F	F	0	one	2	3	four	five	6	7	eight	9	A	B	C	D	E
E	E	F	0	one	2	3	four	five	6	7	eight	9	A	B	C	D
D	D	E	F	0	one	2	3	four	five	6	7	eight	9	A	B	C
C	C	D	E	F	0	one	2	3	four	five	6	7	eight	9	A	B
B	B	C	D	E	F	0	one	2	3	four	five	6	7	eight	9	A
A	A	B	C	D	E	F	0	one	2	3	four	five	6	7	eight	9
9	9	A	B	C	D	E	F	0	one	2	3	four	five	6	7	eight
eight	eight	9	A	B	C	D	E	F	0	one	2	3	four	five	6	7
7	7	eight	9	A	B	C	D	E	F	0	one	2	3	four	five	6
6	6	7	eight	9	A	B	C	D	E	F	0	one	2	3	four	five
five	five	6	7	eight	9	A	B	C	D	E	F	0	one	2	3	four
four	four	five	6	7	eight	9	A	B	C	D	E	F	0	one	2	3
3	3	four	five	6	7	eight	9	A	B	C	D	E	F	0	one	2
2	2	3	four	five	6	7	eight	9	A	B	C	D	E	F	0	one
one	one	2	3	four	five	6	7	eight	9	A	B	C	D	E	F	0
0	0	one	2	3	four	five	6	7	eight	9	A	B	C	D	E	F

C

	one	2	3	four	five	6	7	eight	9	A	B	C	D	E	F
F	one	one	one	one	one	one	one	one	one	one	one	one	one	one	one
E	0	one	one	one	one	one	one	one	one	one	one	one	one	one	one
D	0	0	one	one	one	one	one	one	one	one	one	one	one	one	one
C	0	0	0	one	one	one	one	one	one	one	one	one	one	one	one
B	0	0	0	0	one	one	one	one	one	one	one	one	one	one	one
A	0	0	0	0	0	one	one	one	one	one	one	one	one	one	one
9	0	0	0	0	0	0	one	one	one	one	one	one	one	one	one
eight	0	0	0	0	0	0	0	one	one	one	one	one	one	one	one
7	0	0	0	0	0	0	0	0	one	one	one	one	one	one	one
6	0	0	0	0	0	0	0	0	0	one	one	one	one	one	one
five	0	0	0	0	0	0	0	0	0	0	one	one	one	one	one
four	0	0	0	0	0	0	0	0	0	0	0	one	one	one	one
3	0	0	0	0	0	0	0	0	0	0	0	0	one	one	one
2	0	0	0	0	0	0	0	0	0	0	0	0	0	one	one
one	0	0	0	0	0	0	0	0	0	0	0	0	0	0	one
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Notes

² ¹ ² http://www.computerhistory.org/collections/accession/XD127.80 Computer History Museum
↑ http://www.computer-museum.ru/histussr/setun2.htm Small automatic digital machine "Setun". N. P. Brusentsov, E. A. Zhogolev, V. V. Verigin, S. P. Maslov, A. M. Tishulina
↑ http://spanderashvili.narod.ru/PA.pdf Astrakhan State Technical University, Department of Automated Information Processing Systems and Management, Coursework on the discipline Object-Oriented Programming in the specialty 220200 of Automated Information Processing Systems and Management , Fulfilled Morozov A.V., Spanderashvili D.V., Altufev M.Yu., Checked c.t. n., Assoc. Laptev V.V., Ch. XXIV Threefold adder. Astrakhan-2001
↑ http://www.dcs.gla.ac.uk/~simon/teaching/CS1Q-students/systems/tutorials/tut3sol.pdf CS1Q Computer Systems
↑ http://314159.ru/kushnerov/kushnerov1.pdf Ternary digital technology. Retrospective and Modernity
↑ Threefold ternary (3B BCT) semi-adder in ternary asymmetric number system
↑ Fibonacci computers. Trinity mirror-symmetrical addition and subtraction
↑ M. A. Kartsev. Arithmetic of digital machines. The main editors of the physical and mathematical literature of the publishing house "Nauka", 1969, 576 p. 2. Adders and other schemes for performing elementary operations. 2.3. Single-bit combinational adders for decimal and other number systems. P.71

[autogenerated1-1] ² ¹ ² http://www.computerhistory.org/collections/accession/XD127.80 Computer History Museum

[2] ttp://www.computer-museum.ru/histussr/setun2.htm Small automatic digital machine "Setun". N. P. Brusentsov, E. A. Zhogolev, V. V. Verigin, S. P. Maslov, A. M. Tishulina

[3] ttp://spanderashvili.narod.ru/PA.pdf Astrakhan State Technical University, Department of Automated Information Processing Systems and Management, Coursework on the discipline Object-Oriented Programming in the specialty 220200 of Automated Information Processing Systems and Management , Fulfilled Morozov A.V., Spanderashvili D.V., Altufev M.Yu., Checked c.t. n., Assoc. Laptev V.V., Ch. XXIV Threefold adder. Astrakhan-2001

[4] ttp://www.dcs.gla.ac.uk/~simon/teaching/CS1Q-students/systems/tutorials/tut3sol.pdf CS1Q Computer Systems

[5] ttp://314159.ru/kushnerov/kushnerov1.pdf Ternary digital technology. Retrospective and Modernity

[6] Threefold ternary (3B BCT) semi-adder in ternary asymmetric number system

[7] Fibonacci computers. Trinity mirror-symmetrical addition and subtraction

[8] M. A. Kartsev. Arithmetic of digital machines. The main editors of the physical and mathematical literature of the publishing house "Nauka", 1969, 576 p. 2. Adders and other schemes for performing elementary operations. 2.3. Single-bit combinational adders for decimal and other number systems. P.71

Semi-adder

History

Binary half-adder

Heelometer Stibitsa "Model K Adder"

Threefold half-adder

Decimal semi-adder

Hexadecimal

See also

Notes

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