Harvard architecture

In the 1930s, the US government commissioned Harvard and Princeton universities to develop computer architecture for naval artillery. At the end of the 1930s , Howard Aiken developed the computer architecture of Mark I at Harvard University , later called by the name of this university. The original idea was demonstrated by Aiken of IBM in October 1937 ^[1] . However, the simpler implementation of Princeton University (better known as von Neumann architecture , named after the authoritative consultant scientist and developer who was the first to provide a report ^[2] on architecture, which came during fruitful discussions in the team of creators; the authors the ideas behind this architecture were John Presper Eckert and John William Mockley ).

Harvard architecture was used by the Soviet scientist A. I. Kitov at the VTs-1 of the USSR Ministry of Defense ^[3] .

Typical operations ( addition and multiplication ) require several actions from any computing device:

• a sample of two operands ;
• selection of instructions and its implementation;
• saving the result .

The idea implemented by Aiken was to physically separate the command and data transmission lines. Aiken’s first Mark I computer used perforated tape to store instructions, and electromechanical registers to work with data. This made it possible to simultaneously send and process commands and data, thereby significantly increasing the overall speed of the computer.

In Harvard architecture, the characteristics of memory devices for instructions and memory for data need not be the same. In particular, word width, clocking, implementation technology, and memory address structure may vary. On some systems, instructions may be stored in read-only memory, while data storage typically requires read and write memory. Some systems require significantly more memory for instructions than memory for data, since data can usually be loaded from external or slower memory. Such a need increases the bit width (width) of the instruction memory address bus in comparison with the data memory address bus.

Difference from von Neumann architecture

In a pure von Neumann architecture, a processor at any given time can either read an instruction or read / write a unit of data from / in memory. Both actions cannot occur simultaneously, because instructions and data use the same stream ( bus ).

In a computer using Harvard architecture, the processor can read the next command and operate on data memory simultaneously and without using a cache memory. Thus, a computer with Harvard architecture with a certain complexity of the circuit is faster than a computer with von Neumann architecture, since the flows of commands and data are located on separate physically unconnected hardware channels.

Based on the physical separation of the command and data buses, the bit depths of these buses may vary and physically cannot intersect.

Modified Harvard Architecture

The corresponding memory access implementation scheme has one obvious drawback - high cost. When separating the transmission channels of commands and data on the processor chip, the latter should have almost twice as many interface pins , since the address bus and data bus comprise the bulk of the microprocessor pins. The way to solve this problem was the idea to use a common data bus and address bus for all external data, and inside the processor to use a data bus, command bus and two address buses. This concept was called modified Harvard architecture .

Such circuitry is used in modern signal processors. We went even further towards reducing costs when creating single-chip microcomputers - microcontrollers . In them, one command and data bus is also used inside the crystal.

Separation of buses in a modified Harvard structure is carried out using separate control signals: read, write, or select a memory area.

Extended Harvard Architecture

Often, you need to choose three components: two operands and an instruction (in digital signal processing algorithms this is the most common task in FFT , FIR , and IIR filters). There is a cache for this. An instruction can be stored in it - therefore, both buses remain free and it becomes possible to transfer two operands simultaneously. The use of cache memory along with shared buses is called “Super Harvard Architecture” (“SHARC”), an advanced Harvard architecture.

An example is the “ Analog Devices ” processors: ADSP-21xx - modified Harvard architecture, ADSP-21xxx (SHARC) - extended Harvard architecture.

Hybrid Modifications with von Neumann Architecture

Hybrid architectures exist that combine the strengths of both Harvard and von Neumann architectures. Modern CISC-processors have a separate level 1 cache for commands and data, which allows them to receive both a command and data for its execution in one working cycle. That is, the processor core is hardware Harvard, but it is von Neumann software, which simplifies the writing of programs. Typically, in these processors, one bus is used both for transmitting commands and for transmitting data, which simplifies the system schematically. Modern versions of such processors can sometimes contain integrated controllers of several different types of buses at once for working with various types of memory - for example, DDR RAM and Flash . Nevertheless, in this case, buses are usually used both for transmitting commands and for transmitting data without separation, which makes these processors even closer to the von Neumann architecture while maintaining the advantages of Harvard architecture.

The first computer to use the idea of ​​Harvard architecture was Mark I.

Harvard architecture is used in PLCs and microcontrollers , such as Microchip PIC , Atmel AVR , Intel 4004 , Intel 8051 , as well as in the cache memory of the first level of x86 microprocessors, dividing into two equal or different in volume units for data and commands.

• Von Neumann architecture