Trinity Trigger

In 1956-1958, Nikolai Petrovich Brusentsov with a group of like-minded people ( Faculty of Mechanics and Mathematics of Moscow State University ) built the first serial electronic ternary computer with a positional symmetric ternary number system Setun .

In 1970, Brusentsov from Moscow State University built Setun-70 electronic ternary computers.

The famous Soviet computer specialist Professor D. A. Pospelov wrote: “Barriers that stand in the way of the application of the ternary symmetric number system in computers are technical obstacles. Cost-effective and efficient elements with three stable states have not yet been developed. As soon as such elements are developed, most computers of a universal type and many special computers are likely to be designed so that they function in a ternary symmetrical number system. "

The famous American scientist Donald Knuth expressed the opinion that "the replacement of a binary trigger (" flip-flop ") with a ternary trigger (" flip-flap-flop ") will definitely happen one day." ^[2] (“Flip-flop” means two-stage, “flip-flap-flop” means three-stage, Knut thought “flip-flop” means duality (two-digit), and “flip-flap-flop” means three-way (three-figure) )).

Mechanical ternary counting trigger is used in one-button stopwatch .

Elements and components of ternary computers

Connecting relatively simple logic at the input of a three-bit ternary trigger allows you to create a three-bit ternary D-trigger with three D-inputs (ternary D-trigger) ^[3] .
Three-bit ternary analogs of binary T-flip-flops, ternary data registers , ternary half- adders , ternary totalizers , ternary arithmetic logic devices ( ALU ), ternary processors , ternary static random access memory ( SRAM ), ternary microcontrollers , ternary computers , ternary microcomputers are also possible.

Performance

For one clock cycle, one bit in ternary systems transmits one ternary bit (trit), which has three states, one bit in binary systems transfers one bit, which has two states, that is, one ternary bit transfers in 3/2 = 1.5 (one and a half) times more numbers (codes) than one binary digit.

When using three-bit and two-bit triggers, the number of trigger switches is on average the same as in three-level triggers, but at the output of three-bit and two-bit triggers, the switching frequency in individual lines B2, B1 and B0 is 1/3 less than in a three-level trigger.

When using conventional binary triggers in three-bit and two-bit systems, the switching frequency in lines B2, B1 and B0 is 1/3 less than in a three-level trigger, that is, the use of ordinary binary triggers and ternary triggers on ordinary binary triggers in ternary three-bit and two-bit systems allows you to apply logic elements 1/3 less high-frequency than in a three-level single-wire ternary system.

Hardware Costs

In most cases, when constructing logic circuits on ternary triggers, the hardware costs increase by approximately 2 times compared with ordinary binary triggers and only in very rare cases, when solving problems having threefoldness (Task “Traffic Light” ^[4] ), it is possible to slightly reduce the hardware costs .

Reliability

Since two-level three-bit ternary triggers can work in both three-bit and two-bit modes, in the event of a break in one of the three output lines (conductors), you can switch to two-bit mode, which increases the reliability of devices on these triggers.

In the three-bit mode, when one of the three output conductors is broken, the levels on the remaining two conductors allow full hardware or software recovery of the three-bit code.

The feedback system for all triggers is the same. The output of each of the three elements is connected to the inputs of two other elements. In the triggers on the three elements 3ILI-NOT and on the three elements 3I-NOT, the three input signals are fed to the three inputs of the three elements and the ground. Triggers on the three elements 3ILI-NOT and on the three elements 3I-NOT are switched by applying a switching signal to two of the three inputs. In the triggers on the 4I-NOT elements (SN7420, K155LA1 ^[5] , 164LA8, K176LA8, CD4012, 564LA8, K561LA8, CD4012A, K555LA1) and 4ILI-NOT (164LE6, K176LE6, CD4002, 564LE6, K561BLE, K5616LE, K5616LE, K561LE6 ^6] ) the remaining 6 inputs are combined into three pairs, each of the three pairs is connected to two elements. Three input signals are fed to three combined pairs and ground. Triggers on the three 4I-NOT elements and on the three 4IL-NOT elements are switched by applying a switching signal to one of the three pairs. The output of the triggers is three output buses and a ground (common), like a three-phase electrical network.

Three-digit single-unit ternary triggers on three elements of the 2NI-NOT and a three-digit one-zero ternary trigger on three elements of 2I-NOT is advisable to use in the cells of the ternary static super-operative memory (ternary SRAM ).

Since when “fixing” the storage level at the third input of mounting “1” or mounting “0”, these triggers work like a normal binary asynchronous RS-trigger, these triggers in ternary digital electronics are ternary analogs of the binary asynchronous RS-trigger .

Inputs and outputs

In the ternary analogue of the RS-trigger, there are three inputs: S0 (Set0) - setting to 0 (analogue of the R-input), S1 (Set1) - setting to 1 (analogue of the S-input), S2 (Set2) - setting to 2 (without analogue ) and "ground", and three outputs: Q0 - output of inverter 0 (analog of Q), Q1 output of inverter 1 (analog of inverse Q) and Q2 output of inverter 2 (without analog) and "ground".

Two-Level Trinity Triggers

Two-level ternary triggers are built on two-level elements, and the trinity of work is achieved using a feedback system. Two-level ternary triggers can be two-bit (two-wire two-level ternary system) and three-bit (three-wire two-level ternary system).

Two-level two-wire and three-wire ternary systems are more noise-resistant than a three-level single-wire ternary system, since a three-level single-wire system works up to a relative EMF of the interference signal up to Uп / 4 = 0.25 (up to 25% of Uп), and two-level two-wire and three-wire ternary systems work to the relative EMF of the interference signal up to Up / 2 = 0.5 * Up (up to 50% of Up).

2-level 2-bit

One of the many possible ternary two-bit two-wire coding systems (“-” = {00}, “0” = {01} or {10}, “+” = {11}) was proposed by Carl W. Nelson, Jr. in 1969 ^[7] . Two-bit two-level ternary triggers work in a ternary two-bit two-wire coding system {00}, {01}, {10} and have a three-bit or two-bit input and two-bit output.

As a two-bit ternary trigger, you can use two-level three-bit ternary triggers in two-bit mode (with the TQB2 output disabled).

Two-Level Three-Bit

Three-bit two-level (three-phase ^[8] ) ternary triggers have a unique three-bit input and a unique three-bit output. Two-level allows you to build unique three-bit ternary triggers on the usual elements of two-level logic ( RTL , DTL , TTL , ESL , MOS , CMOS , etc.).

The following unique three-bit ternary triggers are known:

• Three -bit three - bit single - unit trigger on three logical elements 2 OR-NOT ( function f _{2,1,01 10} ) ^[9] .

• One-zero three-bit ternary trigger on three logical elements 2 AND-NOT ( function f _{2,1,07 10} ).

• A single- unit three -bit ternary trigger on three logical elements 3OR-NOT ( function f _{3,1,1 10} ) (trigger from the site of A. P. Stakhov) ^[10] (K155LE4, SN7427).

• One-zero three-bit ternary trigger on three logical elements 3I-NOT ( function f _{3,1,127 10} ) (K155LA4, SN7410).

• Three-bit single-unit trigger 3x2 OR-NOT + 3x2 And L. K. Baxter Larry K. Baxter, Lexington, Mass . Assignee: Shintron Company, Inc., Cambridge, Mass. US Patent 3,764,919 Oct. 9, 1973 Filed: Dec. 22, 1972 Fig. 5 with inverse output.

• Trigger 3x2 AND-NOT + 3x2 OR-NOT by L. K. Baxter (Larry K. Baxter, Lexington, Mass. Assignee: Shintron Company, Inc., Cambridge, Mass. US Patent 3,764,919 Oct. 9, 1973 Filed: Dec. 22, 1972 Fig. 3 ) with inverse input.

• Three -bit three - bit single - unit trigger on three logical elements 4OR-NOT A. Turetski ^[11] , which is in the patent Larry K. Baxter, Lexington, Mass . Assignee: Shintron Company, Inc., Cambridge, Mass. US Patent 3,764,919 Oct. 9, 1973 Filed: Dec. 22, 1972 Fig. 2 is already referred to as widely known.

• One-zero three-bit ternary trigger on three logical elements 4I-NOT (used in the tristable memory cell Takashi Nanya, Tokyo, Japan Assignee: Nippon Electric Company , Limited, Tokyo, Japan US Patent 3,893,086 July 1, 1975 Filed: Dec. 11, 1973 Fig. 2. Block 1) (K155LA1, SN7420), a similar trigger with a slightly complicated control circuit is used in the shift register described in the patent "SU374663 Asynchronous shift register", V. P. Morin and E. E. Popov.

• Three-bit ternary trigger on three logical elements 2I-2I-2ILI-NOT (patent SU661606 Memory cell for buffer register. A. I. Bakhshtab, V. I. Varshavsky, V. B. Marakhovsky, V. A. Peschansky, L. Ya Rosenblum, N. A. Starodubtsev and B. S. Zirlin).
• Three-bit ternary trigger on three logical elements 2I-4ILI-NOT (AS USSR 599332 12/25/76 Trinity trigger. N. G. Korobkov, I. N. Kornet, P. N. Dmitriev, L. V. Korobkova, V. I. Gordienko and V. D. Bliznyuk. Kharkov Aviation Institute) ^[12]

Three-Level Trinity Triggers

Trinity triggers on three-level elements.
In three-level elements, three states correspond to three voltage levels - negative, zero, positive, (low, medium, high).
In ^[13] , Fig. 9 shows a diagram of a “ternary static trigger” on two three-level inverters. This trigger has three states (-1, + 1), (+ 1, -1) and (0,0), but it does not have rotation, but sways like a swing or scales.

Schemes of ternary three-level triggers are also given in ^[14] and ^[15] .

Mixed Trinity Triggers

With a two-level (three-phase) input and with a three-level (single-phase) output

With a three-level (single-phase) input and with a two-level (three-phase) output

The site ^[16] gives a project of a mixed ternary analogue of a binary clocked D-trigger with a sequential clocked three-level D-input and with a parallel two-level (three-phase) output, consisting of 11 blocks, from 3 to 5 transistors in each block, that is, at least 33 transistors per one ternary three-level D-trigger.

The “Ternary code receiver” ^[17] provides a diagram and description of the receiver of consecutive three-level ternary bits in the “ternary polar code” and their conversion to parallel binary two-bit ternary bits, which is a ternary trigger with a single-line three-level input and with a two-line two-bit output with a demultiplexer .

Trinity Data Triggers (D-Triggers)

• Trigger Robert C. Braddock USPat. 3,662,193 May 9, 1972, Filed May 24, 1971 ^[18] link to the prototype from the journal Electronic Design, May 10, 1966, section “Ideas for Design”
• Trinity data triggers (D-triggers) are listed on the Trinity Triggers page.

Trinity Counting Triggers (T-Triggers)

• Trinity counting trigger. USSR AS 764138 11/27/78 N.G. Korobkov, V.I. Gordienko, L.V. Korobkova, N.T. Berezyuk and K.K. Furmanov. Kharkov Aviation Institute. ^[nineteen]
• Trinity counting trigger. USSR AS 780207 12/26/78 N.G. Korobkov, L.V. Korobkova, A.E. Lebedenko, and K.K. Furmanov. Kharkov Aviation Institute N.E. Zhukovsky. ^[20]
• Trinity counting trigger. SU 1078632 12.24.82 N.G. Korobkov, L.V. Korobkova, A.E. Lebedenko and K.K. Furmanov. Kharkov Aviation Institute N.E. Zhukovsky. ^[21]
• Trinity counting trigger. SU 1188887 02/28/84 B.S. Zirlin. Institute of Social and Economic Problems of the Academy of Sciences of the USSR. ^[22]
• Trinity counting trigger. SU 1422405 01.21.87 A. S. Galkin, V. P. Gribok, L. B. Limanovskaya and V. O. Tverdokhlebova ^[23] . When checking the model of the ternary counting trigger on the elements OR-NOT in the Atanua logical real-time simulator, the trigger turned out to be workable.
• The ternary counting triggers are listed on the Ternary triggers page and on the Ternary three-bit counting triggers (T-triggers) page.
• Economical three-bit (3B BCT UU) ternary counting trigger (T-trigger) ^[24]

• Trinity number system
• Trinity rank
• Trinity Logic
• SRAM (memory)
• Trinity SRAM (memory)
• Trinity DRAM
• Ternary computer
• Trinity ADC
• Trinity Algorithms
• Trinity Search
• Trigger
• Register (digital technology)
• Counter (electronics)
• Totalizer # Trinity Totalizer
• Trinity Register
• Ternary memory cell (transfer contents)

• Gurvich I. Multistable potential circuits, - “Devices and control systems”, 1968, No. 10. AS USSR 599332
• Bukhreev I.N. et al. "Microelectronic circuits of digital devices." M., "Owls. Radio ”, 1975, p. 215, Fig. 5.51. AU USSR 599332
• U.S. Patent No. 3508033 1970
• AS of the USSR No. 319078 1971
• USSR AS No. 851785 1979

• Kulikov A. S. Trinity Triggers
• Alexander Kushnerov. Trinity digital technology. Retrospective and modern. // University named after Ben Gurion, Be'er Sheva, Israel. 10/28/05
• Chip of a new current amplifier working in a ternary system.
• Prosser, F. Wu, X. Chen, X. Computers and Digital Techniques, IEE Proceedings E. Sep 1988. Volume: 135, Issue: 5, On page (s): 266-272. “CMOS ternary flip-flops and their applications” Dept. of comput. Sci., Indiana Univ., Bloomington, IN, USA
• Zhuang, N. Wu, H. Electronics Letters. July 19, 1990 Volume: 26, Issue: 15. On page (s): 1145-1146. "Novel ternary JKL flip-flop" Dept. of Electr. Eng., Hangzhou Univ., Zhejiang, China.
• Steve Grubb Steve Grubb Project of elements and nodes of a ternary computer (English)